HSP43220JC-25Z

HSP43220 INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 21

Technical content

Features

• Single Chip Narrow Band Filter with up to 96dB Attenuation
• DC to 33MHz Clock Rate
• 16-Bit 2’s Complement Input
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECIMATE™
• Up to 512 Taps
• Pb-Free Available (RoHS compliant)

Applications

• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
• Large Sample Rate Converter NOTE: DECIMATE Software Development Tool (This software tool may be downloaded from our internet site: www.intersil.com

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP43220JC-25 HSP43220JC-25 0 to +70 84 Ld PLCC N84.1.15 HSP43220JC-25Z HSP43220JC-25Z 0 to +70 84 Ld PLCC (Pb-free) N84.1.15 HSP43220JC-33 HSP43220JC-33 0 to +70 84 Ld PLCC N84.1.15 HSP43220JC-33Z HSP43220JC-33Z 0 to +70 84 Ld PLCC (Pb-free) N84.1.15 NOTE: These Intersil Pb-free plastic packaged products employ special Pb- free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet October 10, 2008 FN2486.10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2000, 2004, 2008. All Rights Reserved DECIMATE™ is a trademark of Intersil Corporation. All other trademarks mentioned are the property of their respective owners.

2 FN2486.10 October 10, 2008 Block Diagram INPUT CLOCK DATA INPUT DATA OUT FIR CLOCK DECIMATION UP TO 1024 DECIMATION UP TO 16 DATA READY CONTROL AND COEFFICIENTS FIR DECIMATION FILTER HIGH ORDER DECIMATION FILTER Pinout HSP43220

84 PLASTIC LEADED CHIP CARRIER (PLCC)

VCC The +5V power supply pins. GND The device ground. CK_IN I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this cl ock signal. The maximum clock frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN can be divided down from FIR_CK. CK_IN is a CMOS level signal. FIR_CK I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal. 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 DATA_IN 1 DATA_IN 0 VCC GND CK_IN VCC GND DATA_IN 2 DATA_IN 3 DATA_IN 4 DATA_IN 5 DATA_IN 6 DATA_IN 7 DATA_IN 8 DATA_IN 9 DATA_IN 10 DATA_IN 11 DATA_IN 12 DATA_IN 13 DATA_IN 14 DATA_IN 15 DATA_OUT 1 DATA_OUT 0 GND DATA_OUT 2 DATA_OUT 3 DATA_OUT 4 DATA_OUT 5 DATA_OUT 6 DATA_OUT 7 DATA_OUT 8 DATA_OUT 9 DATA_OUT 10 DATA_OUT 11 GND V CC DATA_OUT 12 DATA_OUT 13 DATA_OUT 14 DATA_OUT 15 DATA_OUT 16 DATA_OUT 17 C_BUS 15 V CC VCC GND STARTOUT WR CS C_BUS 14 C_BUS 13 C_BUS 12 C_BUS 11 C_BUS 10 C_BUS 9 C_BUS 8 C_BUS 7 C_BUS 6 STARTIN C_BUS 5 C_BUS 4 C_BUS 3 C_BUS 2 C_BUS 1 C_BUS 0 VCC OUT_SELH OUT_ENP OUT_ENX GND DATA_RDY FIR_CK VCC GND DATA_OUT 23 DATA_OUT 22 DATA_OUT 21 DATA_OUT 20 DATA_OUT 19 DATA_OUT 18 RESET ASTARTIN HSP43220

3 FN2486.10 October 10, 2008 The HDF The first filter section is called the High Order Decimation Filter (HDF) and is optimized to perform decimation by large factors. It implements a low pass filter using only adders and delay elements instead of a large number of multiplier/ accumulators that would be required using a standard FIR filter. The HDF is divided into 4 sections: the HDF filter section, the clock divider, the control register logic and the start logic (Figure 1). Data Shifter After being latched into the Input Register the data enters the Data Shifter. The data is positioned at the output of the shifter to prevent errors due to overflow occurring at the output of the HDF. The number of bits to shift is controlled by H_GROWTH. DATA_IN0-15 I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchronous fashion, and is latched on the rising edge of the CK _IN signal. The data bus is in 2's complement fractional format. Bit 15 is the MSB. C_BUS0-15 I Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0 and A1 DATA_OUT 0-23 O Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of the output, DATA_OUT16-23 will provide extension or grow th bits depending on the state of OUT_SELH and whether the FIR has been put in bypass mode. Output bits DATA_OUT0- 15 will provide bits 20 through 2-15 when the FIR is not bypassed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode. DATA_RDY O An active high output strobe that is synchronous with FIR_CK t hat indicates that the result of the just completed FIR cycle is available on the data bus. RESET I RESET is an asynchronous signal which requires that t he input clocks CK_IN and FIR_CK are active when RESET is asserted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path is not initialized. The control register bits that are clear ed are F_BYP , H_STAGES, and H_DRATE. The F_DIS bit is set. In order to guarantee consistent operation of the part, the user must reset the DDF after power-up. WR I Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of WR will latch the C_BUS0-15 data into the register specified by A0 and A1. CS I Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate register as specified by A0 and A1. A0, A1 I Control Register Address. These lines are decoded to determin e which control register is the destination for the data on C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs. ASTARTIN I ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT. STARTOUT O STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of CK_IN. STARTIN I STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's. OUT_SELH I Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from the accumulator output. Processing is not interrupted by this pin. OUT_ENP I Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin. OUT_ENX I Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin. Pin Description (Continued) NAME TYPE DESCRIPTION HSP43220

comb section in bypass mode. stage the output of the register is subtracted from the input. DEC) should not exceed 4MHz. F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK. with a 3-bit fractional part in 2's complement format. internal start signal (see “Start Logic” on page 9). A0 and A1 is loaded with the data on the C_BUS. FIGURE 3. COMB FILTER

6 FN2486.10 October 10, 2008 DDF Control Registers F_Register (A1 = 0, A0 = 0) FIGURE 4. F_OAD F_BYP F_ESYM F_DRATE F_TAPS F A 0 F B 0 E S 0 D 3D 2D 1D 0T 8T 7T 6T 5T 4T 3T 2T 1T 0 F_TAPS Bits T0-T8 are used to specify the number of FIR filter taps. The number entered is one less than the number of taps required. For example, to specify a 511 tap filter F_TAPS would be programmed to 510. The minimum number of FIR taps = 3 (F_TAPS = 2). F_DRATE Bits D0-D3 are used to specify the amount of FIR decimation. The number entered is one less than the decimation required. For example, to specify decimation of 16, F_DRATE would be programmed to 15. For no FIR decimation, F_DRATE would be set equal to 0. FDRATE +1 is defined as F DEC. F_ESYM Bit ES0 is used to select the FIR symmetry. F_ESYM is set equal to one to select even symmetry and set equal to zero to select odd symmetry. When F_ESYM is one, data is added in the pre-adder; when it is zero, data is subtracted. Normally set to one. F_BYP FB0 is used to select FIR bypass mode. FIR bypass mode is selected by setting F_BYP = 1. When FIR bypass mode is selected, the FIR is internally set up for a 3 tap even symmetric filter, no decimation (F_DRATE = 0) and F_OAD is set equal to one to zero one side of the preadder. In FIR bypass mode all FIR filter parameters, except F_CLA, are ignored, including the contents of the FIR coefficient RAM. In FIR bypass mode the output data is brought output on the lower 16 bits of the output bus DATA_OUT 0-15. To disable FIR bypass mode, F_BYP is set equal to zero. When F_BYP is returned to zero, the coefficients must be reloaded. F_OAD Bit FA0 is used to select the zero the preadder mode. This mode zeros one of the inputs to the pre-adder. Zero preadder mode is selected by setting F_OAD equal to one. This feature is useful when implementing arbitrary phase filters or can be used to verify the filter coefficients. To disable the Zero Preadder mode F_OAD is set equal to zero. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSP43220

7 FN2486.10 October 10, 2008 FC_Register (A1 = 0, A0 = 1) FIGURE 5. DDF Control Registers (Continued) F_CF C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 XXXXXXXXXXXX C 3 C 2 C 1 C 0 F_CF Bits C0-C19 represent the coefficient data, where C19 is the MSB. Two writes are required to write each coefficient which is 2's complement fractional format. The first write loads C19 through C4; C3 through C0 are loaded on the second write cycle. As the coefficients are written into this register they are formatted into a 20-bit coefficient and written into the Coefficient RAM sequentially starting with address location zero. The coefficients must be loaded sequentially, with the center tap being the last coefficient to be loaded. See “Coefficient RAM” on page 10. 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 HSP43220

8 FN2486.10 October 10, 2008 H_Register 1 (A1 = 1, A0 = 0) FIGURE 6. DDF Control Registers (Continued) RESERVED F_DIS F_CLA H_BYP H_DRATE F D 0 F C 0 H B 0 R 9R 8R 7R 6R 5R 4R 3R 2R 1R 0 1 5 1 4 1 3 1 2 1 1 1 0 987654321 0 H_DRATE Bits R0-R9 are used to select the amount of decimation in the HDF. The amount of decimation selected is programmed as the required decimation minus one; for instance to select decimation of 1024 H_DRATE is set equal to 1023. HDRATE +1 is defined as H DEC. H_BYP Bit HB0 is used to select HDF bypass mode. This mode is selected by setting H_BYP = 1. When this mode is selected the input data passes through the HDF unfiltered. Internally H_STAGES and H_DRATE are both set to zero and H_GROWTH is set to 50. H_REGISTER 2 must be reloaded when H_BYP is returned to 0. To disable HDF bypass mode H_BYP = 0. The relationship between CK_IN and FIR_CK in this and all other modes is defined by Equation 2. F_CLA Bit FC0 is used to select the clear accumulator mode in the FIR. This mode is enabled by setting F_CLA = 1 and is disabled by setting F_CLA = 0. In normal operation this bit should be set equal to zero. This mode zeros the feedback path in the accumulator of the multiplier/accumulator (MAC). It also allows the multiplier output to be clocked off the chip by FIR_CK, thus DATA_RDY has no meaning in this mode. This mode can be used in conjunction with the F_OAD bit to read out the FIR coefficients from the coefficient RAM. F_DIS Bit FD0 is used to select the FIR disable mode. This feature enables the FIR parameters to be changed. This feature is selected by setting F_DIS = 1. This mode terminates the current FIR cycle. While this feature is selected, the HDF continues to process data and write it into the FIR data RAM. When the FIR re-programming is completed, the FIR can be re-enabled either by clearing F_DIS, or by asserting one of the start inputs, which automatically clears F_DIS. HSP43220

10 FN2486.10 October 10, 2008 Coefficient RAM The Coefficient RAM stores the coefficients for the current FIR filter being implemented. The coefficients are loaded into the Coefficient RAM over the control bus (C_BUS). The coefficients are written into the Coefficient RAM sequentially, starting at location zero. It is only necessary to write one half of the coefficients when symmetric filters are being implemented, where the last coefficient to be written in is the center tap. The coefficients are loaded into address 01 in two writes. The first write loads the upper 16 bits of the 20-bit coefficient, C4 through C19. The second write loads the lower 4 bits of the coefficient, C0 through C3, where C19 is the MSB. The two 16-bit writes are then formatted into the 20-bit coefficient that is then loaded into the Coefficient RAM starting at RAM address location zero, where the coefficient at this location is the outer tap (or the first coefficient value). To reload coefficients, the Coefficient RAM Address pointer must be reset to location zero so that the coefficients will be loaded in the order the FIR filter expects. There are two methods that can be used to reset the Coefficient RAM address pointer. The first is to assert RESET, which automatically resets the pointer, but also clears the HDF and alters some of the control register bits. ( RESET does not change any of the coefficient values.) The second method is to set the F_DIS bit in control register H_ REGISTER1. This control bit allows any of the FIR control register bits to be re- programmed, but does not automatically modify any control registers. When the programming is completed, the FIR is re-started by clearing the F_DIS bit or by asserting one of the start inputs ( ASTARTIN or STARTIN). The F_DIS bit allows the filter parameters to be changed more quickly and is thus the recommended reprogramming method. Data RAM The Data RAM stores the data needed for the filter calculation. The format of the data is: where the sign bit is in the 20 location. The 16-bit output of the HDF Output Register is written into the Data Ram on the rising edge of CK_DEC. RESET initializes the write pointer to the data RAM. After a RESET occurs, the output of the FIR will not be valid until the number of new data samples written to the Data RAM equals TAPS. The filter always operates on the most current sample and the taps-1 previous samples. Thus if the F_DIS bit is set, data continues to be written into the data RAM coming from the HDF section. When the FIR is enabled again the filter will be operating on the most current data samples and thus another transient response will not occur. The maximum throughput of the FIR filter is limited by the use of a single Multiplier/Accumulator (MAC). The data output from the HDF being clocked into the FIR filter by CK_DEC must not be at a rate that causes an erroneous result being calculated because data is being overwritten. Equation 2 describes the relationship between, FIR_CK, CK_DEC, the number of taps that can be implemented in the FIR, the decimation rate in the HDF and the decimation rate in the FIR. (In the Design Considerations section of the “Operational Section” on page 12 there is a chart that shows the tradeoffs between these parameters.) This equation expresses the minimum FIR_CK. The minimum FIR_CK is the smallest integer multiple of CK_IN that satisfies Equation 1. In addition, the TSK specification must be met (see AC Electrical Specifications). FDEC is the decimation rate in the FIR (FDEC = F_DRATE +1), where TAPS = the number of taps in the FIR for even length filters and equals the number of taps+1 for odd length filters. Solving Equation 3 for the maximum number of taps: In using this equation, it must be kept in mind that CK_IN/ HDEC must be less than or equal to 4MHz (unless the HDF is in bypass mode in which case this limitation in the HDF does not apply). In the “Operational Section” on page 12 under the Design Considerations, there is a table that shows the trade-offs of these parameters. In addition, Intersil provides a software package called DECI MATE™ which designs the DDF filter from System specifications. The registered outputs of the data RAM are added or subtracted in the 17-bit pre-adder. The F_OAD control bit allows zeros to be input into one side of the pre-adder. This provides the capability to implement non-symmetric filters. The selection of adding the register outputs for an even symmetric filter or for subtracting the register outputs for odd symmetric filter is provided by the control bit F_ESYM, which is programmed over the control bus. When subtraction is selected, the new data is subtracted from the old data. The 17-bit output of the adder forms one input of the multiplier/accumulator. A control bit F_CLA provides the capability to clear the feedback path in the accumulator such that multiplier output will not be accumulated, but will instead flow directly to the output register. The bit weightings of the data and coefficients as they are processed in the FIR is shown as follows. Input Data (from HDF) 20.2-1 . . . 2-15 Pre-adder Output 2120.2-1 . . . 2-15 Coefficient 20.2-1 . . . 2-19 FIR_CK CK_IN TAPS/2() 4F DEC++[] HDEC FDEC TAPS 2 FIR_CK H DEC FDEC ⎛⎞= (EQ. 3) HSP43220

used to load the output data into an external register or RAM. FIGURE 9. FIR FILTER

FIGURE 14. DIGITAL CHANNELIZER TABLE 1. DESIGN TRADE OFF FOR MINIMUM HDEC NOTE: Filter not realizable.

15 FN2486.10 October 10, 2008 DECIMATE Intersil provides a development system which assists the design engineer to utilizing this filter. The DECIMATE software package provides the user with both filter design and simulation environments for filter evaluation and design. These tools are integrated within one standard DSP CAD environment, The Athena Group's Monarch Professional DSP Software package. The software package is designed specifically for the DDF. It provides all the filter design software for this proprietary architecture. It provides a user-friendly menu driven interface to allow the user to input system level filter requirements. It provides the frequency response curves and a data flow simulation of the specified filter design (Figure 15). It also creates all the information necessary to program the DDF, including a PROM file for programming the control registers. This software package runs on an IBM™ PC™, XT™, AT™, PS/2™ computer or 100% compatible with the following configuration: 640k RAM 5.25” or 3.5” Floppy drive hard disk math co-processor MS/PC-DOS 2.0 or higher CGA, MCGA, EGA, VGA and Hercules graphics adapters For more information, see the description of DECIMATE in “DECIMATE” on page 15. HSP43220

FIGURE 15. DECIMATE DESIGN MODULE SCREENS

17 FN2486.10 October 10, 2008 Absolute Maximum Ratings TA = +25°C Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (°C/W) Maximum Junction Temperature http://www.intersil.com/pbfree/Pb-FreeReflow.asp Die Characteristics CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V High Level Clock Input VIHC VCC = 5.25V 3.0 - V Low Level Clock Input VILC VCC = 4.75V - 0.8 V Output HIGH Voltage VOH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current II VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current IO VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.25V, (Note 3) - 500 µA Operating Power Supply Current ICCOP f = 15MHz, VIN = VCC or GND, VCC = 5.25V, (Notes 2, 4) - 120 mA Capacitance TA = +25°C, (Note 3) PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance CIN FREQ = 1MHz, VCC = Open, All measurements are referenced to device ground - 12 pF Output Capacitance CO - 10 pF NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 8mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and CL = 40pF. HSP43220

18 FN2486.10 October 10, 2008 tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER SYMBOL NOTES -15 -25 -33 UNITSMIN MAX MIN MAX MIN MAX Input Clock Frequency FCK 0 15 0 25.6 0 33 MHz FIR Clock Frequency FFIR 0 15 0 25.6 0 33 MHz Input Clock Period tCK 66 - 39 - 30 - ns FIR Clock Period tFIR 66 - 39 - 30 - ns Clock Pulse Width Low tSPWL 26 - 16 - 13 - ns Clock Pulse Width High tSPWH 26 - 16 - 13 - ns Clock Skew Between FIR_CK and CK_IN tSK 0 tFIR - 25 0 tFIR - 15 0 tFIR - 15 ns CK_IN Pulse Width Low tCH1L (Notes 5, 8) 29 - 19 - 19 - ns CK_IN Pulse Width High tCH1H (Notes 5, 8) 29 - 19 - 19 - ns CK_IN Setup to FIR_CK tCIS (Notes 5, 8) 27 - 17 - 17 - ns CK_IN Hold from FIR_CK tCIH (Notes 5, 8) 2 - 2 - 2 - ns RESET Pulse Width Low tRSPW 4tCK - 4tCK - 4tCK - ns Recovery Time on RESET tRTRS 8tCK - 8tCK - 8tCK - ns ASTARTIN Pulse Width Low tAST tCK + 10 - tCK + 10 - tCK + 10 - ns STARTOUT Delay from CK_IN tSTOD - 35 - 20 - 18 ns STARTIN Setup to CK_IN tSTIC 25 - 15 - 10 - ns Setup Time on DATA_IN tSET 20 - 15 - 14 - ns Hold Time on All inputs tHOLD 0 - 0 - 0 - ns Write Pulse Width Low tWL 26 - 15 - 12 - ns Write Pulse Width High tWH 26 - 20 - 18 - ns Setup Time on Address Bus Before the Rising Edge of Write tSTADD 26 - 20 - 20 - ns Setup Time On-chip Select Before the Rising Edge of Write tSTCS 26 - 20 - 20 - ns Setup Time on Control Bus Before the Rising Edge of Write tSTCB 26 - 20 - 20 - ns DATA_RDY Pulse Width Low tDRPWL 2tFIR - 20 - 2tFIR - 10 - 2tFIR - 10 - ns DATA_OUT Delay Relative to FIR_CK tFIRDV - 50 - 35 - 28 ns DATA RDY Valid Delay Relative to FIR_CK tFIRDR - 35 - 25 - 20 ns DATA_OUT Delay Relative to OUT_SELH tOUT - 25 - 20 - 20 ns Output Enable to Data Out Valid tOEV (Note 6) - 15 - 15 - 15 ns Output Disable to Data Out Three-State tOEZ (Note 5) - 15 - 15 - 15 ns Output Rise, Output Fall Times tr, tf from 0.8V to 2V, (Note - 8 - 8 - 6 ns NOTES: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 6. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with and CL = 40pF. 7. AC Testing is performed as follows: Input levels (CLK Input) 4.0V and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels (CLK) = 2.0V, (Others) = 1.5V, Output load per test load circuit and CL = 40pF. 8. Applies only when H_BYP = 1 or H_DRATE = 0. HSP43220

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2486.10 October 10, 2008 HSP43220 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0. 25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N84.1.15 (JEDEC MS-018AF ISSUE A)

84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N8 4 8 4 6 Rev. 2 11/97