HSP43220JC-25

HSP43220_04 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 18

Technical content

Features

• Single Chip Narrow Band Filter with up to 96dB Attenuation
• DC to 33MHz Clock Rate
• 16-Bit 2’s Complement Input
• 20-Bit Coefficients in FIR
• 24-Bit Extended Precision Output
• Programmable Decimation up to a Maximum of 16,384
• Standard 16-Bit Microprocessor Interface
• Filter Design Software Available DECIMATE™
• Up to 512 Taps

Applications

• Very Narrow Band Filters
• Zoom Spectral Analysis
• Channelized Receivers
• Large Sample Rate Converter Block Diagram

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP43220JC-25 0 to 0 84 Ld PLCC N84.1.15 HSP43220JC-33 0 to 70 84 Ld PLCC N84.1.15 DECIMATE Software Development Tool (This software tool may be downloaded from our Internet site: www.intersil.com) INPUT CLOCK DATA INPUT DATA OUT FIR CLOCK DECIMATION UP TO 1024 DECIMATION UP TO 16 DATA READY CONTROL AND COEFFICIENTS FIR DECIMATION FILTER HIGH ORDER DECIMATION FILTER Data Sheet July 2004 FN2486.9 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2000, 2004. All Rights Reserved DECIMATE™ is a trademark of Intersil Corporation.

84 PLASTIC LEADED CHIP CARRIER (PLCC)

VCC The +5V power supply pins. GND The device ground. CK_IN I Input Sample Clock. Operations in the HDF are synchronous with the rising edge of this clock signal. The maximum clock frequency is 33MHz. CK_IN is synchronous with FIR_CK and thus the two clocks may be tied together if required, or CK_IN can be divided down from FIR_CK. CK_IN is a CMOS level signal. FIR_CK I Input Clock for the FIR Filter. This clock must be synchronous with CK_IN. Operations in the FIR are synchronous with the rising edge of this clock signal. The maximum clock frequency is 33MHz. FIR_CK is a CMOS level signal. DATA_IN0- I Input Data Bus. This bus is used to provide the 16-bit input data to the HSP43220. The data must be provided in a synchro- nous fashion, and is latched on the rising edge of the CK_IN signal. The data bus is in 2's complement fractional format. Bit 15 is the MSB. C_BUS0-15 I Control Input Bus. This input bus is used to load all the filter parameters. The pins WR, CS and A0, A1 are used to select the destination of the data on the Control bus and write the Control bus data into the appropriate register as selected by A0 and A1 DATA_OUT 0-23 O Output Data Bus. This 24-Bit output port is used to provide the filtered result in 2's complement format. The upper 8 bits of the output, DATA_OUT16-23 will provide extension or grow th bits depending on the state of OUT_SELH and whether the FIR has been put in bypass mode. Output bits DATA_OUT0-15 will provide bits 20 through 2-15 when the FIR is not by - passed and will provide the bits 2-16 through 2-31 when the FIR is in bypass mode. DATA_RDY O An active high output strobe that is synchronous with FIR_CK t hat indicates that the result of the just completed FIR cycle is available on the data bus. 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 DATA_IN 1 DATA_IN 0 VCC GND CK_IN VCC GND DATA_IN 2 DATA_IN 3 DATA_IN 4 DATA_IN 5 DATA_IN 6 DATA_IN 7 DATA_IN 8 DATA_IN 9 DATA_IN 10 DATA_IN 11 DATA_IN 12 DATA_IN 13 DATA_IN 14 DATA_IN 15 DATA_OUT 1 DATA_OUT 0 GND DATA_OUT 2 DATA_OUT 3 DATA_OUT 4 DATA_OUT 5 DATA_OUT 6 DATA_OUT 7 DATA_OUT 8 DATA_OUT 9 DATA_OUT 10 DATA_OUT 11 GND V CC DATA_OUT 12 DATA_OUT 13 DATA_OUT 14 DATA_OUT 15 DATA_OUT 16 DATA_OUT 17 C_BUS 15 V CC VCC GND STARTOUT WR CS C_BUS 14 C_BUS 13 C_BUS 12 C_BUS 11 C_BUS 10 C_BUS 9 C_BUS 8 C_BUS 7 C_BUS 6 STARTIN C_BUS 5 C_BUS 4 C_BUS 3 C_BUS 2 C_BUS 1 C_BUS 0 VCC OUT_SELH OUT_ENP OUT_ENX GND DATA_RDY FIR_CK VCC GND DATA_OUT 23 DATA_OUT 22 DATA_OUT 21 DATA_OUT 20 DATA_OUT 19 DATA_OUT 18 RESET ASTARTIN HSP43220

The first filter section is called the High Order Decimation Filter (HDF) and is optimized to perform decimation by large factors. It implements a low pass filter using only adders and delay elements instead of a large number of multiplier/ accumulators that would be required using a standard FIR filter. The HDF is divided into 4 sections: the HDF filter section, the clock divider, the control register logic and the start logic (Figure 1). Data Shifter After being latched into the Input Register the data enters the Data Shifter. The data is positioned at the output of the shifter to prevent errors due to overflow occurring at the output of the HDF. The number of bits to shift is controlled by H_GROWTH. Integrator Section The data from the shifter goes to the Integrator section. This is a cascade of 5 integrat or (or accumulator) stages, which implement a low pass filter. Each accumulator is implemented as an adder followed by a register in the feed forward path. The integrator is clocked by the sample clock, CK_IN as shown in Figure 2. The bit width of each integrator stage goes from 66 bits at the first integrator down to 26 bits at the output of the fifth integrator. Bit truncation is performed at each integrator stage because the data in the integrator stages is being accumulated and thus is growing, therefore the lower bits become insignificant, and can be truncated without losing significant data. RESET I RESET is an asynchronous signal which requires that t he input clocks CK_IN and FIR_CK are active when RESET is as- serted. RESET disables the clock divider and clears all of the internal data registers in the HDF. The FIR filter data path is not initialized. The control register bi ts that are cleared are F_BYP, H_STAGES, and H_DRATE. The F_DIS bit is set. In order to guarantee consistent operation of the part, the user must reset the DDF after power up. WR I Write Strobe. WR is used for loading the internal registers of the HSP43220. When CS and WR are asserted, the rising edge of WR will latch the C_BUS0-15 data into the register specified by A0 and A1. CS I Chip Select. The Chip Select input enables loading of the internal registers. When CS and WR are low, the A0 and A1 address lines are decoded to determine the destination of the data on C_BUS0-15. The rising edge of WR then loads the appropriate reg- ister as specified by A0 and A1. A0, A1 I Control Register Address. These lines are decoded to determin e which control register is th e destination for the data on C_BUS0-15. Register loading is controlled by the A0 and A1, WR and CS inputs. ASTARTIN I ASTARTIN is an asynchronous signal which is sampled on the rising edge of CK_IN. It is used to put the DDF in operational mode. ASTARTIN is internally synchronized to CK_IN and is used to generate STARTOUT. STARTOUT O STARTOUT is a pulse generated from the internally synchronized version of ASTARTIN. It is provided as an output for use in multi-chip configurations to synchronously start multiple HSP43220's. The width of STARTOUT is equal to the period of CK_IN. STARTIN I STARTIN is a Synchronous Input. A high to low transition of this signal is required to start the part. STARTIN is sampled on the rising edge of CK_IN. This synchronous signal can be used to start single or multiple HSP43220's. OUT_SELH I Output Select. The OUT_SELH input controls which bits are provided at output pins DATA_OUT16-23. A HIGH on this control line selects bits 28 through 21 from the accumulator output. A LOW on this control line selects bits 2-16 through 2-23 from the accumulator output. Processing is not interrupted by this pin. OUT_ENP I Output Enable. The OUT_ENP input controls the state of the lower 16 bits of the output data bus, DATA_OUT0-15. A LOW on this control line enables the lower 16 bits of the output bus. When OUT_ENP is HIGH, the output drivers are in the high imped- ance state. Processing is not interrupted by this pin. OUT_ENX I Output Enable. The OUT_ENX input controls the state of the upper 8 bits of the output data bus, DATA_OUT16-23. A LOW on this control line enables the upper 8 bits of the output bus. When OUT_ENX is HIGH, the output drivers are in the high impedance state. Processing is not interrupted by this pin. Pin Description (Continued) NAME TYPE DESCRIPTION HSP43220

DEC) should not exceed 4MHz. F_TAPS, F_DRATE, H_DRATE, CK_IN and FIR_CK. with a 3-bit fractional part in 2's complement format. started by an internal start signal (see Start Logic). A0 and A1 is loaded with the data on the C_BUS. FIGURE 3. COMB FILTER

F_Register (A1 = 0, A0 = 0) FIGURE 4. F_OAD F_BYP F_ESYM F_DRATE F_TAPS F A 0 F B 0 E S 0 D 3D 2D 1D 0T 8T 7T 6T 5T 4T 3T 2T 1T 0 F_TAPS Bits T0-T8 are used to specify the number of FIR filter taps. The number entered is one less than the number of taps required. For example, to specify a 511 tap filter F_TAPS would be programmed to 510. The mini- mum number of FIR taps = 3 (F_TAPS = 2). F_DRATE Bits D0-D3 are used to specify the amount of FIR decimation. The num- ber entered is one less than the dec imation required. For example, to specify decimation of 16, F_DRATE would be programmed to 15. For no FIR decimation, F_DRATE would be se t equal to 0. FDRATE +1 is defined as FDEC. F_ESYM Bit ES0 is used to select the FIR symmetry. F_ESYM is set equal to one to select even symmetry and set equal to zero to select odd symmetry. When F_ESYM is one, data is added in the pre-adder; when it is zero, data is subtracted. Normally set to one. F_BYP FB0 is used to select FIR bypass mode. FIR bypass mode is selected by setting F_BYP = 1. When FIR bypass mode is selected, the FIR is inter- nally set up for a 3 tap even symmetric filter, no decimation (F_DRATE = 0) and F_OAD is set equal to one to zero one side of the preadder. In FIR bypass mode all FIR filter parameters, except F_CLA, are ignored, includ- ing the contents of the FIR coefficient RAM. In FIR bypass mode the out- put data is brought output on t he lower 16 bits of the output bus DATA_OUT 0-15. To disable FIR bypa ss mode, F_BYP is set equal to zero. When F_BYP is returned to zero, the coefficients must be reloaded. F_OAD Bit FA0 is used to select the zero the preadder mode. This mode zeros one of the inputs to the pre-adder. Ze ro preadder mode is selected by setting F_OAD equal to one. This feature is useful when implementing arbitrary phase filters or can be used to verify the filter coefficients. To disable the Zero Preadder mode F_OAD is set equal to zero. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HSP43220

The coefficients are loaded into address 01 in two writes. The first write loads the upper 16 bits of the 20-bit coefficient, C4 through C19. The second write loads the lower 4 bits of the coefficient, C0 through C3, where C19 is the MSB. The two 16-bit writes are then formatted into the 20-bit coefficient that is then loaded into the Coefficient RAM starting at RAM address location zero, where the coefficient at this location is the outer tap (or the first coefficient value). To reload coefficients, the Coefficient RAM Address pointer must be reset to location zero so that the coefficients will be loaded in the order the FIR filter expects. There are two methods that can be used to reset the Coefficient RAM address pointer. The first is to assert RESET, which automatically resets the pointer, but also clears the HDF and alters some of the control register bits. ( RESET does not change any of the coefficient values.) The second method is to set the F_DIS bit in control register H_ REGISTER1. This control bit allows any of the FIR control register bits to be re- programmed, but does not automatically modify any control registers. When the programming is completed, the FIR is re-started by clearing the F_DIS bit or by asserting one of the start inputs ( ASTARTIN or STARTIN). The F_DIS bit allows the filter parameters to be changed more quickly and is thus the recommended reprogramming method. Data RAM The Data RAM stores the data needed for the filter calculation. The format of the data is: where the sign bit is in the 20 location. The 16-bit output of the HDF Output Register is written into the Data Ram on the rising edge of CK_DEC. RESET initializes the write pointer to the data RAM. After a RESET occurs, the output of the FIR will not be valid until the number of new data samples written to the Data RAM equals TAPS. The filter always operates on the most current sample and the taps-1 previous samples. Thus if the F_DIS bit is set, data continues to be written into the data RAM coming from the HDF section. When the FIR is enabled again the filter will be operating on the most current data samples and thus another transient response will not occur. The maximum throughput of the FIR filter is limited by the use of a single Multiplier/Accumulator (MAC). The data output from the HDF being clocked into the FIR filter by CK_DEC must not be at a rate that causes an erroneous result being calculated because data is being overwritten. The equation shown below describes the relationship between, FIR_CK, CK_DEC, the number of taps that can be implemented in the FIR, the decimation rate in the HDF and the decimation rate in the FIR. (In the Design Considerations section of the OPERATIONAL SECTION there is a chart that shows the tradeoffs between these parameters.) This equation expresses the minimum FIR_CK. The minimum FIR_CK is the smallest integer multiple of CK_IN that satisfies Equation 1. In addition, the TSK specification must be met (see AC Electrical Specifications). F DEC is the decimation rate in the FIR (FDEC = F_DRATE +1), where TAPS = the number of taps in the FIR for even length filters and equals the number of taps+1 for odd length filters. Solving the above equation for the maximum number of taps: In using this equation, it must be kept in mind that CK_IN/ HDEC must be less than or equal to 4MHz (unless the HDF is in bypass mode in which case this limitation in the HDF does not apply). In the OPERATIONAL SECTION under the Design Considerations, there is a table that shows the trade- offs of these parameters. In addition, Intersil provides a software package called DECI MATE™ which designs the DDF filter from System specifications. The registered outputs of the data RAM are added or subtracted in the 17-bit pre-adder. The F_OAD control bit allows zeros to be input into one side of the pre-adder. This provides the capability to implement non-symmetric filters. The selection of adding the register outputs for an even symmetric filter or for subtracting the register outputs for odd symmetric filter is provided by the control bit F_ESYM, which is programmed over the control bus. When subtraction is selected, the new data is subtracted from the old data. The 17-bit output of the adder forms one input of the multiplier/accumulator. A control bit F_CLA provides the capability to clear the feedback path in the accumulator such that multiplier output will not be accumulated, but will instead flow directly to the output register. The bit weightings of the data and coefficients as they are processed in the FIR is shown below. Input Data (from HDF) 20.2-1 . . . 2-15 Pre-adder Output 2120.2-1 . . . 2-15 Coefficient 20.2-1 . . . 2-19 FIR Output The 40 most significant bits of the accumulator are latched into the output register. The lower 3 bits are not brought to the output. The 40 bits out of the output register are selected to be output by a pair of multiplexers. This register is clocked by FIR_CK (see Figure 9). FIR_CK CK_IN TAPS/2() 4F DEC++[] HDEC FDEC TAPS 2 FIR_CK H DEC FDEC = (EQ. 2) HSP43220

The scenario to put the DDF into operational mode is: reset the DDF by asserting the RESET input, configure the DDF over the control bus, and apply a start signal, either by ASTARTIN or STARTIN. Until the DDF is put in operational mode with a start pulse, the DDF ignores all data inputs. To use the asynchronous start, an asynchronous active low pulse is applied to the ASTARTIN input. ASTARTIN is internally synchronized to the sample clock, CK_IN, and generates STARTOUT. This signal is also used internally when the asynchronous mode is selected. It puts the DDF in operational mode and allows the DDF to begin accepting data. When the ASTARTIN input is being used, the STARTIN input must be tied high to ensure proper operation. To start the DDF synchronously, the STARTIN is asserted with a active low pulse that has been externally synchronized to CK_IN. Internally the DDF then uses this start pulse to put the DDF in operate mode and start accepting data inputs. When STARTIN is used to start the DDF the ASTARTIN input must be tied high to prevent false starts. Multi-Chip Start Configurations Since there are two methods to start up the DDF, there are also two configurations that can be used to start up multiple chips. The first method is shown in Figure 12. The timing of the STARTOUT circuitry starts the second DDF on the same clock as the first. If more DDFs are also to be started synchronously, STARTOUT is connected to their STARTIN's. The second method to start up DDFs in a multiple chip configuration is to use the synchronous start scenario. The STARTIN input is wired to all the chips in the chain, and is asserted by a active low synchronous pulse that has been externally synchronized to CK_IN. In this way all DDFs are synchronously started. The ASTARTIN input on all the chips is tied high to prevent false starts. The STARTOUT outputs are all left unconnected. This configuration is illustrated in Figure 13. INPUT DATA FORMAT Fractional Two's Complement Input 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 FIR COEFFICIENT FORMAT Fractional Two's Complement Input 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 OUTPUT DATA FORMAT Fractional Two's Complement Output FOR: OUT_SELH = 1, F_BYP = 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -28 27 26 25 24 23 22 21 20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 FOR: OUT_SELH = 0, F_BYP = 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 -20 . 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 FOR: OUT_SELH = X, F_BYP = 1 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 FIGURE 11. HSP43220

and simulation environments for filter evaluation and design. the Development Tools Section of this data book. TABLE 1. DESIGN TRADE OFF FOR MINIMUM HDEC NOTE: Filter not realizable.

FIGURE 15. DECIMATE DESIGN MODULE SCREENS

Absolute Maximum Ratings TA = 25°C Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (°C/W) Maximum Junction Temperature (PLCC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V High Level Clock Input VIHC VCC = 5.25V 3.0 - V Low Level Clock Input VILC VCC = 4.75V - 0.8 V Output HIGH Voltage VOH IOH = -400µA, VCC = 4.75V 2.6 - V Output LOW Voltage VOL IOL = +2.0mA, VCC = 4.75V - 0.4 V Input Leakage Current II VIN = VCC or GND, VCC = 5.25V -10 10 µA I/O Leakage Current IO VOUT = VCC or GND, VCC = 5.25V -10 10 µA Standby Power Supply Current ICCSB VIN = VCC or GND VCC = 5.25V, Note 3 - 500 µA Operating Power Supply Current ICCOP f = 15MHz, VIN = VCC or GND, VCC = 5.25V, Notes 2 and 4 - 120 mA Capacitance TA = 25°C, Note 3 PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Input Capacitance CIN FREQ = 1MHz, VCC = Open, All measurements are referenced to device ground - 12 pF Output Capacitance CO - 10 pF NOTES: 2. Power supply current is proportional to operating frequency. Typical rating for ICCOP is 8mA/MHz. 3. Not tested, but characterized at initial design and at major process/design changes. 4. Output load per test load circuit with switch open and CL = 40pF. HSP43220

-15 -25 -33 UNITSMIN MAX MIN MAX MIN MAX Input Clock Frequency FCK 0 15 0 25.6 0 33 MHz FIR Clock Frequency FFIR 0 15 0 25.6 0 33 MHz Input Clock Period tCK 66 - 39 - 30 - ns FIR Clock Period tFIR 66 - 39 - 30 - ns Clock Pulse Width Low tSPWL 26 - 16 - 13 - ns Clock Pulse Width High tSPWH 26 - 16 - 13 - ns Clock Skew Between FIR_CK and CK_IN tSK 0 tFIR-25 0 tFIR-15 0 tFIR-15 ns CK_IN Pulse Width Low tCH1L Notes 5, 8 29 - 19 - 19 - ns CK_IN Pulse Width High tCH1H Notes 5, 8 29 - 19 - 19 - ns CK_IN Setup to FIR_CK tCIS Notes 5, 8 27 - 17 - 17 - ns CK_IN Hold from FIR_CK tCIH Notes 5, 8 2 - 2 - 2 - ns RESET Pulse Width Low tRSPW 4tCK - 4tCK - 4tCK - ns Recovery Time on RESET tRTRS 8tCK - 8tCK - 8tCK - ns ASTARTIN Pulse Width Low tAST tCK+10 - tCK+10 - tCK+10 - ns STARTOUT Delay from CK_IN tSTOD - 35 - 20 - 18 ns STARTIN Setup to CK_IN tSTIC 25 - 15 - 10 - ns Setup Time on DATA_IN tSET 20 - 15 - 14 - ns Hold Time on All inputs tHOLD 0 - 0 - 0 - ns Write Pulse Width Low tWL 26 - 15 - 12 - ns Write Pulse Width High tWH 26 - 20 - 18 - ns Setup Time on Address Bus Before the Rising Edge of Write tSTADD 26 - 20 - 20 - ns Setup Time on Chip Select Before the Rising Edge of Write tSTCS 26 - 20 - 20 - ns Setup Time on Control Bus Before the Rising Edge of Write tSTCB 26 - 20 - 20 - ns DATA_RDY Pulse Width Low tDRPWL 2tFIR-20 - 2tFIR-10 - 2tFIR-10 - ns DATA_OUT Delay Relative to FIR_CK tFIRDV - 50 - 35 - 28 ns DATA RDY Valid Delay Relative to FIR_CK tFIRDR - 35 - 25 - 20 ns DATA_OUT Delay Relative to OUT_SELH tOUT - 25 - 20 - 20 ns Output Enable to Data Out Valid tOEV Note 6 - 15 - 15 - 15 ns Output Disable to Data Out Three-State tOEZ Note 5 - 15 - 15 - 15 ns Output Rise, Output Fall Times tr, tf from 0.8V to 2V, Note 5 - 8 - 8 - 6 ns NOTES: 5. Controlled by design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design changes. 6. Transition is measured at ±200mV from steady state voltage with loading as specified in test load circuit with and CL = 40pF. 7. AC Testing is performed as follows: Input levels (CLK Input) 4.0V and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels (CLK) = 2.0V, (Others) = 1.5V, Output load per test load circuit and CL = 40pF. 8. Applies only when H_BYP = 1 or H_DRATE = 0. HSP43220