HSP43216VC-52

HSP43216 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 19

Technical content

Features

• Sample Rates to 52 MSPS
• Architected to Support Sample Rates to 104 MSPS Using External Multiplexer
• Four Modes of Operation: - Interpolate by 2 Filtering - Decimate by 2 Filtering - Quadrature to Real Signal Conversion S/4 Quadrature Down Conversion Followed by Decimate by 2 Filtering
• 16-Bit Inputs and Outputs
• 67-Tap Halfband FIR Filter with 20-Bit Coefficients
• Two’s Complement or Offset Binary Outputs
• Programmable Rounding on Outputs
• 1.24:1 Filter Shape Factor
• >90dB Stopband Attenuation
• <0.0003dB Passband Ripple
• Saturation Logic on Output

Applications

• Digital Down Conversion
• D/A and A/D pre/post Filtering
• Tuning Bandwidth Expansion for HSP45116 and HSP45106 Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE TYPE PKG. NO. HSP43216GC-52 0 to 70 85 Ld CPGA G85.A HSP43216JC-52 0 to 70 84 Ld PLCC N84.1.15 HSP43216VC-52 0 to 70 100 Ld MQFP Q100.14x20 INPUT DATA FLOW CONTROLLER fS/4 QUADRATURE PROCESSOR 67-TAP PROCESSOR fS/4 QUADRATURE UP CONVERT PROCESSOR OUTPUT DATA FLOW CONTROLLER/ FORMATTER AIN0-15 BIN0-15 AOUT0-15 BOUT0-15 MODE0-1 SYNC USB/LSB INT/EXT RND0-2 FMT DOWN CONVERT HALFBAND FILTER OEA OEB CLK Data Sheet January 1999 File Number 3365.7 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

85 PIN PGA

MODE1AIN15AIN12AIN11AIN8AIN5AIN3AIN2FMT VCC AIN0 AIN1 AIN4 AIN7 AIN6 AIN13 MODE AIN10 AIN14 AOUT8 AOUT9 AOUT AOUT6 AOUT5 AOUT7 AOUT AOUT AOUT AOUT AOUT GND OEA AOUT AOUT GND AOUT4 A B C D E F G H J K L 1 1 1 0 987654321 1 1 1 0 987654321 A B C D E F G H J K L LSB PIN ‘A1’ ID EXT AIN9 15 13 12 10 8 41 2 0 14 11 9 53 0 31 76 2 11 12 13 14 15 BOUTBOUT BOUTBOUT AOUT2AOUT0BOUTBOUTBOUT9 BOUT7 BOUT8GND BOUT5 BOUT6 BOUT4 BOUT3 BOUT2 BOUT1 BOUT0 VCC OEB GND RND2 RND1 BIN15 BIN14 BIN12 BIN9 BIN11 BIN5 BIN2 BIN0 INT/ VCC RND0 BIN13 BIN10 BIN6 BIN4 BIN1 USB/ SYNC GND BIN8 BIN7 BIN3 INDEX PIN CLK MODE1 AIN15 AIN12 AIN11 AIN8 AIN5 AIN3 AIN2 FMT VCCAIN0AIN1AIN4AIN7AIN6AIN13 AIN9AIN10AIN14 AOUT8 AOUT9 AOUT AOUT6 AOUT5 AOUT7 AOUT AOUT AOUTAOUT GNDOEA AOUT3AOUT1 GNDAOUT4 A B C D E F G H J K L 1110987654321 1110987654321 A B C D E F G H J K L LSB EXT PIN ‘A1’ ID 10 12 13 15 11 14 1213 AOUT 15 14 MODE HSP43216

100 LEAD MQFP

Pinouts (Continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100 32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931 VCC NC NC NC NC SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 NC NC NC NC BOUT14 BOUT13 BOUT12 BOUT11 BOUT10 GND BOUT9 BOUT8 BOUT7 BOUT6 BOUT5 BOUT4 BOUT3 BOUT2 BOUT1 BOUT0 V CC GND OEB RND2 VCC FMT OEA GND AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0 GND NC NC NC NC BOUT15 NC NC NC NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN9 AIN8 AIN7 AIN6 AIN5 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 GND MODE1 MODE0 CLK HSP43216

84 LEAD PLCC

Pinouts (Continued) AIN0 AIN1 AIN2 AIN3 AIN4 AIN9 AIN8 AIN7 AIN6 AIN5 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 GND MODE1 MODE0 BOUT15 BOUT14 BOUT13 BOUT12 BOUT11 BOUT10 GND BOUT9 BOUT8 BOUT7 BOUT6 BOUT5 BOUT4 BOUT3 BOUT2 BOUT1 BOUT0 V CC GND OEB RND2 SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 V CC FMT OEA GND AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0 GND VCC CLK 1 1 1 0 987654321 8 4 8 3 8 2 8 1 8 0 7 9 7 8 7 7 7 6 7 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Description NAME TYPE DESCRIPTION VCC - +5V Power. GND - Ground. CLK I Clock Input. (CMOS LEVEL). f S is the frequency of CLK AIN0-15 I Input Data Bus A. AIN0 is the LSB. Input data format is 16-bit Two’s Complement. BIN0-15 I Input Data Bus B. BIN0 is the LSB. Input data format is 16-bit Two’s Complement. MODE0-1 I The Mode Select Inputs set one of four operational modes as highlighted in Table 1. INT/EXT I The Internal\\External multiplexer select inputs set whether the data multiplex/demultiplex function required in the various operational modes is performed internally (High State) or externally to the chip (Low State). SYNC I This input is used to synchronize the input sample stream with the zero degree phase of the up or down convert Local Oscillators. In the straight decimate modes, this input can be use to synchronize the input sample stream with a particular phase of the halfband filter. (See the Operational Modes Section for additional information). USB/LSB I The Upper and Lower Sideband select line is used to specify the direction of frequency translation imparted on the data stream in the Down Convert and Decimate Mode and in the Quadrature to Real Convert Mode. (See Operational Modes Section for additional information). RND0-2 I The Round Select inputs set the number of output bits from eight (RND = 000) to sixteen (RND = 110). Least significant output bits are zeroed. See Table 4. OEA I Three-State Control Output Bus A, OUTA0-15. Active Low. OEB I Three-State Control Output Bus B, OUTB0-15. Active Low. FMT I The Format select input is used to convert the two’s complement output to offset binary (unsigned). When asserted high, the AOUT15 and BOUT15 bits are inverted from the normal two’s complement representation. AOUT0-15 O Output Bus A. AOUT0 is the LSB. BOUT0-15 O Output Bus B. BOUT0 is the LSB. HSP43216

Figure 1. The Halfband Filter Processor operates stand Quadrature to Real Conversion. samples at half of the input data rate. † Indicates elements which operate at CLK/2 when theINT/EXT control input is high. FIGURE 1. HALFBAND BLOCK DIAGRAM TABLE 1. MODE SELECT TABLE

00 Decimate by Two

01 Interpolate by Two

10 Down Convert and Decimate

11 Quadrature to Real Conversion

exponential as described in the Operational Modes section. block on the upper and lower processing legs respectively. comprised of even and odd tap filters as shown in Figure 1. even indexed coefficients (even phase) of the halfband filter. phase) of the halfband filter. Table 3. Table 2 shows the different modes and the related frequency with which the spectra in Figure 2 is normalized. Processor for the various modes. CLKs with respect to the operating mode. TABLE 2. NORMALIZED FREQRUENCY vs MODE FIGURE 2. FREQUENCY RESPONSE OF 67-TAP HALFBAND

TABLE 3. FREQUENCY RESPONSE OF THE 67-TAP HALFBAND FILTER NORMALIZED TO THE MODE SPECIFIC SAMPLE RATE

implementation shown in Figure 6. of polyphase filters running at one half of the input data rate. not discarded by the decimation process. TABLE 5. OUTPUT ROUNDING CONTROL

000 Round output to 8 bits, AOUT15-8 and BOUT15-8,

001 Round output to 9 bits, AOUT15-7 and BOUT15-7,

010 Round output to 10 bits, AOUT15-6 and BOUT15-6,

011 Round output to 11 bits, AOUT15-5 and BOUT15-5,

100 Round output to 12 bits, AOUT15-4 and BOUT15-4,

101 Round output to 14 bits, AOUT15-2 and BOUT15-2,

110 Round output to 16 bits, AOUT15-0 and BOUT15-0. FIGURE 5. TRANSVERSAL IMPLEMENTATION OF DECI- FIGURE 6. POLYPHASE IMPLEMENTATION OF DECIMATE

data stream at the interpolated rate. for the attenuation of one half caused by interpolation.

7 TAP HALFBAND FILTER

FIGURE 9. TRANSVERSAL IMPLEMENTATION OF FIGURE 10. POLYPHASE IMPLEMENTATION OF INTERPOLATE

BOUT0-15 precede those on AOUT0-15 in sample order.

9 CLK’s and the pipeline delay through the lower processing

has no effect on part operation. by the down conversion process. implementation using a 7 tap filter as shown in Figure 13. processing elements used in the previous two modes. FIGURE 12. DOWN CONVERT AND DECIMATE OPERATION

an interpolated output data rate of up to 104 MSPS. input is used as described in the preceding paragraph. FIGURE 22. DATA SYNCHRONIZATION WITH PROCESSING

Absolute Maximum Ratings Thermal Information Operating Conditions oC to 70oC Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) Maximum Junction Temperature oC (PLCC and MQFP Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK Frequency 52MHz INT/EXT = ‘1’, Notes 2, 4 - 468 mA VCC = Max, CLK Frequency 52MHz INT/EXT = ‘0’, Notes 3, 4 - 572 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Clock Input High V IHC VCC = Max 3.0 - V Clock Input Low V ILC VCC = Min - 0.8 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -3mA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance C IN CLK Frequency 1MHz, All measurements ref- erenced to GND. TA = 25oC, Note 5 -1 2 p F Output Capacitance C OUT -1 2 p F NOTES: 2. Power supply current is proportional to frequency. Typical rating is 9mA/MHz when Internal Multiplexing is selected,INT/EXT = 1. 3. Power supply current is proportional to frequency. Typical rating is 11mA/MHz when External Multiplexing is selected,INT/EXT = 0. 4. Output load per test circuit and CL = 40pF . 5. Not tested, but characterized at initial design and at major process/design changes. 6. Maximum junction temperature must be considered when operating part at high clock frequencies. HSP43216

NOTE: Test head capacitance. PARAMETER SYMBOL NOTES 52MHz UNITSMIN MAX CLK Period t CP 19 - ns CLK High t CH 7- n s CLK Low t CL 7- n s Setup Time AIN0-15, BIN0-15 to CLK t DS 7- n s Hold Time AIN0-15, BIN0-15 from CLK t DH 0- n s MODE0-1, RND0-2, INT/EXT,SYNC, USB/LSB Setup Time to CLK t RS 7- n s MODE0-1, RND0-2, INT/EXT,SYNC, USB/LSB Hold Time to CLK t RH 0- n s CLK to AOUT0-15, BOUT0-15 Delay t DO -9 n s Output Enable Time t OE -9 n s Output Disable Time t OD Note 8 - 9 ns Output Rise, Output Fall Times t r, tf Note 8 - 5 ns NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. EQUIVALENT CIRCUIT C L (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR I CCSB AND ICCOP HSP43216

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FIGURE 23. TIMING RELATIVE TO CLK FIGURE 24. OUTPUT RISE AND FALL TIMES