HSP43216JC-52Z

HSP43216_08 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 20

Technical content

Features

• Sample Rates to 52MSPS
• Architected to Support Samp le Rates to 104MSPS Using External Multiplexer
• Four Modes of Operation: - Interpolate by 2 Filtering - Decimate by 2 Filtering - Quadrature to Real Signal Conversion S/4 Quadrature Down Conversion Followed by Decimate by 2 Filtering
• 16-Bit Inputs and Outputs
• 67-Tap Halfband FIR Filter with 20-Bit Coefficients
• Two’s Complement or Offset Binary Outputs
• Programmable Rounding on Outputs
• 1.24:1 Filter Shape Factor
• >90dB Stopband Attenuation
• <0.0003dB Passband Ripple
• Saturation Logic on Output
• Pb-Free Available (RoHS Compliant)

Applications

• Digital Down Conversion
• D/A and A/D pre/post Filtering
• Tuning Bandwidth Expansion for HSP45116 and HSP45106

Ordering Information

TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP43216JC-52 HSP 43216JC-52 0 to +70 84 Ld PLCC N84.1.15 HSP43216JC-52Z (Note) HSP43216JC-52Z 0 to +70 84 Ld PLCC (Pb-free) N84.1.15 HSP43216VC-52 HSP 43216VC-52 0 to +70 100 Ld MQFP Q100.14x20 HSP43216VC-52Z (Note) HSP 43216VC-52Z 0 to +70 100 Ld MQFP (Pb-free) Q100.14x20 NOTE: These Intersil Pb-free plas tic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020 Data Sheet October 6, 2008 FN3365.10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2007, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN3365.10 October 6, 2008 Block Diagram INPUT DATA FLOW CONTROLLER fS/4 QUADRATURE PROCESSOR 67-TAP PROCESSOR fS/4 QUADRATURE UP CONVERT PROCESSOR OUTPUT DATA FLOW CONTROLLER/ FORMATTER AIN0-15 BIN0-15 AOUT0-15 BOUT0-15 MODE0-1 SYNC USB/LSB INT/EXT RND0-2 FMT DOWN CONVERT HALFBAND FILTER OEA OEB CLK Pinouts HSP43216JC (100 LD MQFP) TOP VIEW 99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100 32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931 VCC NC NC NC NC SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 NC NC NC NC BOUT14 BOUT13 BOUT12 BOUT11 BOUT10 GND BOUT9 BOUT8 BOUT7 BOUT6 BOUT5 BOUT4 BOUT3 BOUT2 BOUT1 BOUT0 V CC GND OEB RND2 VCC FMT OEA GND AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0 GND NC NC NC NC BOUT15 NC NC NC NC AIN0 AIN1 AIN2 AIN3 AIN4 AIN9 AIN8 AIN7 AIN6 AIN5 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 GND MODE1 MODE0 CLK HSP43216

3 FN3365.10 October 6, 2008 HSP43216 (84 LD PLCC) TOP VIEW Pinouts (Continued) AIN0 AIN1 AIN2 AIN3 AIN4 AIN9 AIN8 AIN7 AIN6 AIN5 AIN15 AIN14 AIN13 AIN12 AIN11 AIN10 GND MODE1 MODE0 BOUT15 BOUT14 BOUT13 BOUT12 BOUT11 BOUT10 GND BOUT9 BOUT8 BOUT7 BOUT6 BOUT5 BOUT4 BOUT3 BOUT2 BOUT1 BOUT0 V CC GND OEB RND2 SYNC USB/LSB INT/EXT BIN0 BIN1 BIN2 BIN3 BIN4 BIN5 BIN6 BIN7 BIN8 BIN9 BIN10 BIN11 BIN12 BIN13 BIN14 BIN15 RND0 RND1 V CC FMT OEA GND AOUT15 AOUT14 AOUT13 AOUT12 AOUT11 AOUT10 AOUT9 AOUT8 AOUT7 AOUT6 AOUT5 AOUT4 AOUT3 AOUT2 AOUT1 AOUT0 GND VCC CLK 1 11 0 9 8 7 6 5 4 3 2 1 8 48 38 28 18 07 97 87 77 67 5 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 Pin Description NAME TYPE DESCRIPTION VCC - +5V Power. GND - Ground. CLK I Clock Input. (CMOS LEVEL). f S is the frequency of CLK AIN0-15 I Input Data Bus A. AIN0 is the LSB. Input data format is 16-bit Two’s Complement. BIN0-15 I Input Data Bus B. BIN0 is the LSB. Input data format is 16-bit Two’s Complement. MODE0-1 I The Mode Select Inputs set one of four operational modes as highlighted in Table 1. INT/EXT I The Internal\\External multiplexer select inputs set whether t he data multiplex/demultiplex function required in the various operational modes is performed internally (High State) or externally to the chip (Low State). SYNC I This input is used to synchronize the input sample str eam with the zero degree phase of the up or down convert Local Oscillators. In the straight decimate modes, this input can be use to synchronize the input sample stream with a particular phase of the halfband filter. (See the Operational Modes Section for additional information). USB/LSB I The Upper and Lower Sideband select line is used to specify the direction of frequency translation imparted on the data stream in the Down Convert and Decimate Mode and in the Quadrature to Real Convert Mode. (See Operational Modes Section for additional information). RND0-2 I The Round Select inputs set the number of output bits fr om eight (RND = 000) to sixteen (RND = 110). Least significant output bits are zeroed. See Table 4. OEA I Three-State Control Output Bus A, OUTA0-15. Active Low. OEB I Three-State Control Output Bus B, OUTB0-15. Active Low. FMT I The Format select input is used to convert the two’s comple ment output to offset binary (unsigned). When asserted high, the AOUT15 and BOUT15-bits are inverted from the normal two’s complement representation. AOUT0-15 O Output Bus A. AOUT0 is the LSB. BOUT0-15 O Output Bus B. BOUT0 is the LSB. HSP43216

Figure 1. The Halfband Filter Processor operates stand Quadrature to Real Conversion. samples at half of the input data rate. † Indicates elements which operate at CLK/2 when the INT/EXT control input is high. FIGURE 1. HALFBAND BLOCK DIAGRAM TABLE 1. MODE SELECT TABLE

00 Decimate by Two

01 Interpolate by Two

10 Down Convert and Decimate

11 Quadrature to Real Conversion

exponential as described in the Operational Modes section. block on the upper and lower processing legs respectively. comprised of even and odd tap filters as shown in Figure 1. even indexed coefficients (even phase) of the halfband filter. Table 3. Table 2 shows the different modes and the related frequency with which the spectra in Figure 2 is normalized. Processor for the various modes. CLKs with respect to the operating mode. TABLE 2. NORMALIZED FREQUENCY vs MODE FIGURE 2. FREQUENCY RESPO NSE OF 67-TAP HALFBAND

TABLE 3. FREQUENCY RESPONSE OF THE 67-TAP HALFBAND FILTER NORMALIZED TO THE MODE SPECIFIC SAMPLE RATE

implementation shown in Figure 6. of polyphase filters running at one half of the input data rate. TABLE 5. OUTPUT ROUNDING CONTROL

000 Round output to 8-bits, AOUT15-8 and BOUT15-8, zero

001 Round output to 9-bits, AOUT15-7 and BOUT15-7, zero

010 Round output to 10-bits, AOUT15-6 and BOUT15-6,

011 Round output to 11-bits, AOUT15-5 and BOUT15-5,

100 Round output to 12-bits, AOUT15-4 and BOUT15-4,

101 Round output to 14-bits, AOUT15-2 and BOUT15-2,

110 Round output to 16-bits, AOUT15-0 and BOUT15-0. FIGURE 5. TRANSVERSAL IMPLEMENTATION OF FIGURE 6. POLYPHASE IMPLEMENTATION OF DECIMATE

original transversal filter. for the attenuation of one half caused by interpolation.

7 TAP HALFBAND FILTER

FIGURE 9. TRANSVERSAL IMPLEMENTATION OF FIGURE 10. POLYPHASE IMPLEMENTATION OF

BOUT0-15 precede those on AOUT0-15 in sample order.

9 CLK’s and the pipeline delay through the lower processing

has no effect on part operation. by the down conversion process. implementation using a 7 tap filter as shown in Figure 13. processing elements used in the previous two modes. FIGURE 12. DOWN CONVERT AND DECIMATE OPERATION

an interpolated output data rate of up to 104 MSPS. input is used as described in the preceding paragraph. FIGURE 22. DATA SYNCHRONIZATION WITH PROCESSING

16 FN3365.10 October 6, 2008 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θ JA (°C/W) θJC (°C/W) Maximum Junction Temperature Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, CLK Frequency 52MHz INT/EXT = ‘1’, Notes 2, 4 -4 6 8 m A VCC = Max, CLK Frequency 52MHz INT/EXT = ‘0’, Notes 3, 4 -5 7 2 m A Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 μA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 μA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 μA Clock Input High V IHC VCC = Max 3.0 - V Clock Input Low V ILC VCC = Min - 0.8 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -3mA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance C IN CLK Frequency 1MHz, All measurements referenced to GND. TA = +25°C, Note 5 -1 2 p F Output Capacitance C OUT -1 2 p F NOTES: 2. Power supply current is proportional to frequency. Typical rating is 9mA/MHz when Internal Multiplexing is selected, INT/EXT = 1. 3. Power supply current is proportional to frequency. Typical rating is 11mA/MHz when External Multiplexing is selected, INT/EXT = 0. 4. Output load per test circuit and C L = 40pF. 5. Not tested, but characterized at initial design and at major process/design changes. 6. Maximum junction temperature must be consider ed when operating part at high clock frequencies. HSP43216

17 FN3365.10 October 6, 2008 AC Test Load Circuit NOTE: Test head capacitance. PARAMETER SYMBOL NOTES 52MHz UNITSMIN MAX CLK Period t CP 19 - ns CLK High t CH 7- n s CLK Low t CL 7- n s Setup Time AIN0-15, BIN0-15 to CLK t DS 7- n s Hold Time AIN0-15, BIN0-15 from CLK t DH 0- n s MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Setup Time to CLK t RS 7- n s MODE0-1, RND0-2, INT/EXT, SYNC, USB/LSB Hold Time to CLK t RH 0- n s CLK to AOUT0-15, BOUT0-15 Delay t DO -9 n s Output Enable Time t OE -9 n s Output Disable Time t OD Note 8 - 9 ns Output Rise, Output Fall Times t r, tf Note 8 - 5 ns NOTES: Test VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 8. Controlled via design or process paramete rs and not directly tested. Characterized upon initial design and after major process and/or changes. EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP HSP43216

19 FN3365.10 October 6, 2008 HSP43216 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0 .25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N84.1.15 (JEDEC MS-018AF ISSUE A)

84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N8 4 8 4 6 Rev. 2 11/97

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3365.10 October 6, 2008 HSP43216 Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40

0.016 MIN

L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008

0.20 A-B SD SCM

0.076 0.003 -C- -D- -H- Q100.14x20 (JEDEC MS-022GC-1 ISSUE B)

100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE

A - 0.134 - 3.40 - A2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - D 0.908 0.918 23.08 23.32 3 D1 0.782 0.792 19.88 20.12 4, 5 E 0.673 0.681 17.10 17.30 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.029 0.040 0.73 1.03 - N 100 100 7 e 0.026 BSC 0.65 BSC - ND 30 30 - NE 20 20 - Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toleranc es per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-