HSP43168 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 25
Technical content
Features
- Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR
- 10-Bit Data and Coefficients
- On-Board Storage for 32 Programmable Coefficient Sets
- Up To: 256 FIR Taps, 16x16 2-D Kernels, or 10x19-Bit Data and Coefficients
- Programmable Decimation to 16
- Programmable Rounding on Output
- Standard Microprocessor Interface
- Pb-Free Available (RoHS Compliant)
Applications
- Quadrature, Complex Filtering
- Image Processing
- Polyphase Filtering
- Adaptive Filtering
Ordering Information
TEMP. RANGE (°C) PACKAGE PKG. DWG. # HSP43168VC-45 HSP43168VC-45 0 to +70 100 Ld MQFP Q100.14x20 HSP43168VC-45Z (Note) HSP43168VC-45Z 0 to +70 100 Ld MQFP (Pb-free) Q100.14x20 HSP43168JC-33 HSP43168JC-33 0 to +70 84 Ld PLCC N84.1.15 HSP43168JC-33Z (Note) HSP43168JC-33Z 0 to +70 84 Ld PLCC N84.1.15 NOTE: These Intersil Pb-free plas tic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2000, 2001, 2004, 2007, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. Data Sheet July 27, 2009 FN2808.12
2 FN2808.12 July 27, 2009 Block Diagram Pinouts HSP43168 (84 LD PLCC) TOP VIEW FIR CELL A COEFFICIENT BANK A CIN0 - 9 A0 - 8 WR INA0 - 9 OUT9 - 27 CONTROL/ CONFIGURATION MUX / ADDER 91 9 INB0 - 9/ OUT0 - 8 OEH OEL CSEL0 - 4 MUX MUX FIR CELL B COEFFICIENT BANK B INB 2 INB 3 INB 4 INB 5 INB 6 INB 8 INB 7 GND OUT 13 OUT 12 OUT 11 OUT 9 INB 1 INB 0 OUT 10 V CC OUT 14 OUT 15 GND OUT 16 OEL RVRS FWD TXFR OUT 27 OUT 26 OUT 25 OUT 24 OUT 23 OUT 22 OUT 21 OUT 20 OUT 19 OUT 17 V CC VCC OEH GND ACCEN CLK OUT 18 SHFTEN CIN 6 CIN 2 INA 9 INA 7 INA 6 INA 5 INA 3 CIN 7 CIN 4 GND CIN 3 CIN 0 VCC INA 2 INA 1 INA 0 INB 9 CIN 5 CIN 1 INA 8 INA 4 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 4950 51 52 53 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 767778 75 A 4 A 6 A 7 CSEL 3 A 5 A 3 A 0 CSEL 4 CIN 9 A 2 CIN 8 CSEL 1 CSEL 0 A 8 A 1 GND MUX 1 MUX 0 CSEL 2 VCC WR HSP43168
3 FN2808.12 July 27, 2009 HSP43168 (100 LD MQFP) TOP VIEW Pinouts (Continued) 99 98 97 96 95 94 93 91 89 87 85 84 83 818286889092100 32 33 34 35 36 37 38 40 42 44 46 47 48 50494543413931 WR VCC VCC CIN9 GND GND CSEL0 CSEL1 CSEL2 CSEL3 CSEL4 INA5 CIN0 INA9 INA8 INA7 INA6 V CC VCC INA4 INA3 CIN1 INA1 INA0 INA2 NC CIN7 NC CIN6 CIN5 GND CIN4 GND CIN3 CIN2 CIN8 NC NC INB7 INB9 INB8 OUT18 OUT17 NC V CC GND GND V CC OUT19 GND OEH OUT27 OUT26 OUT24 OUT23 OUT22 OUT21 OUT20 OUT25 GND MUX0 RVRS NC FWRD TXFR ACCEN V CC VCC CLK SHIFTEN MUX1 INB6 GND GND INB5 INB4 INB3 INB2 INB1 INB0 OEL OUT9 OUT10 VCC VCC OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 HSP43168
4 FN2808.12 July 27, 2009 Pin Description SYMBOL TYPE DESCRIPTION VCC VCC: +5V power supply pin GND Ground CIN0-9 I Control/Coefficient Data Bus. Processor interface for loading control data and coefficients. CIN0 is the LSB A0-8 I Control/Coefficient Address Bus. Processor interface for addressing Control and Coefficient Registers. A0 is the LSB WR I Control/Coefficient Write Clock. Data is latched into t he Control and Coefficient Registers on the rising edge of WR CSEL0-4 I Coefficient Select. This input dete rmines which of the 32 coefficient sets are to be used by FIR A and B. This input is registered and CSEL0 is the LSB. INA0-9 I Input to FIR A. INA0 is the LSB INB0-9 I/O Bidirectional Input for FIR B. INB0 is the LSB and is input only. When used as output, INB1-9 are the LSBs of the output bus, and INB9 is the MSB of these bits. OUT9-27 O 19 MSBs of Output Bus. Data format is either unsigned or two's complement depending on configuration. OUT27 is the MSB. SHFTEN I Shift Enable. This active low input en ables clocking of data into the part and shifting of data through the Decimation Registers. FWRD FWD I Forward ALU Input Enable. When active low, data from t he forward decimation path is input to the ALUs through the “a” input. When high, the “a” inputs to the ALUs are zeroed. RVRS I Reverse ALU Input Enable. When active low, data from the reverse decimation path is input to the ALUs through the “b” input. When high, the “b” inputs to the ALUs are zeroed. TXFR I Data Transfer Control. This active low input switches t he LIFO being read into the reverse decimation path with the LIFO being written from the forward decimation path (see Figure 1). MUX0-1 I Adder/Mux Control. This input controls data flow through the output Adder/Mux. Table 5 lists the various configurations. CLK I Clock. All inputs except those associated with the processor interface (CIN0-9, A0-8, WR) and the output enables (OEL, OEH) are registered by the rising edge of CLK. OEL I Output Enable Low. This three-state control enables the LSBs of the output bus to INB1-9 when OEL is low. OEH I Output Enable High. This three-state control enables OUT9-27 when OEH is low. ACCEN I Accumulate Enable. This active hi gh input allows accumulation in the FIR Cell Accumulator. A low on this input latches the FIR Accumulator contents into the Output Holding Registers while zeroing the feedback pass in the Accumulator. NC No connect HSP43168
FIGURE 1. DUAL FIR FILTER
filters with 10-bit data and 20-bit coefficients or vice versa. Control Registers, and 2) loading the FIR Filter Coefficients. which clocks the address and configuration data into the part. “Microprocessor Interface” on page 6. “Coefficient Bank” on page 8. asserted in a manner determined by the application. control can be found in “Output MUX/Adder” on page 9. for loading data into the Control Block and Coefficient Banks. control and coefficient data loading is asynchronous to CLK. “Coefficient Bank” on page 8). Table 2. Writing to any of the Control/Configuration Registers Register can be written to during reset. FIGURE 2. LATCHING C9-0 VALUES INTO ADDRESS A8-0
between filter taps as shown in Equation 1. independent operation. Bit 9 must be programmed to 0. signal is delayed by only three CLKS (see Figure 1). For odd-taps, the TXFR signal is delayed by four CLKS. 9 are used to support programmable rounding on the output. added with the result from the other FIR cell. configure the part for actual decimation applications. TABLE 1. CONFIGURATION/CONTROL WORD 0 BIT 4 Mode Select 0 = Single Filter Mode.
5 Odd/Even Filter
0 = Even Symmetric Coefficients. 1 = Odd Symmetric Coefficients.
6 FIR A Odd/Even
0 = Odd Number of Taps in Filter. 1 = Even Number of Taps in Filter.
7 FIR B Odd/Even
(Defined Same as FIR A Above). 8 FIR B Input Source 0 = Input from INA0-9. 9 Not Used Set to 0 for Proper Operation. TABLE 2. CONFIGURATION/CONTROL WORD 1 BIT 0 FIR A Input Format 0 = Unsigned. 1 FIR A Coefficient Format (Defined same as FIR A input). 2 FIR B Input Format (Defined same as FIR A input). 3 FIR B Coefficient (Defined same as FIR A input).
4 Data Reversal Enable
- Address locations 002H to 011H are reserved, and writing to
“Application Examples” on page 10). operation has begun will invalidate the filtering result. for filtering applications which do not use decimation. sample into the forward decimation path. fourth delay stage in FIR A's forward path to FIR B. paths feed the “a” and “b” inputs of the ALUs respectively. operation if configured for odd symmetric coefficients. Control Word 0, Bit 5 is used to set the ALU operation. would appear on the ALU output. of 8 coefficients (4 coefficients for FIR A and 4 for FIR B). CSEL0-4 is used to select a coefficient set to be used. polyphase filtering operations. TABLE 3. ALU CONFIGURATIONS
multiplier in FIR B in the second coefficient set. accumulator is latched into the Output Holding Registers. contents of the Output Holding Registers remain unchanged. sum the output of each FIR cell. select is set to 1 and MUX1-0 is set to 00. TABLE 4. FIR COEFFICIENT WRITE ADDRESSES TABLE 5. MUX1-0 BIT DEFINITIONS
00 FIRA + FIRB (FIR B Scaled by 2 -10)
01 FIRA + FIRB
10 FIRA
11 FIRB
required and the MUX1-0 control values for each filter example. Figure 5. Each of the FIR cells takes advantage of using the multipliers in both cells. Figure 7. The Block Diagrams in Figure 7 are a simplification of show the data flow through one of the two FIR cells. given by the equation at the bottom of each block diagram. adders for the data/coefficient alignment shown in Figure 6. reversal will produce erroneous results. stored coefficient set, in this example CSEL = 00000. TABLE 7. CONFIGURATION CONTROL REGISTER VALUES FIGURE 5. USING HSP43168 AS TWO INDEPENDENT FILTERS FIGURE 6. DATA/COEFFICIENT ALIGNMENT FOR 8-TAP
8 TAPS
21 FN2808.12 July 27, 2009 Absolute Maximum Ratings Thermal Information Operating Conditions Die Characteristics Maximum Junction Temperature http://www.intersil.com/pbfree/Pb-FreeReflow.aspCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty NOTE: 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max (Notes 4, 5, 6) CLK Frequency 33MHz - 363 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 µA Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 µA Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 µA Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -400µA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 2mA, VCC = Min - 0.4 V Clock Input High V IHC VCC = Max 3.0 - V Clock Input Low V ILC VCC = Min - 0.8 V Input Capacitance C IN CLK Frequency 1MHz All measurements referenced to GND. TA = +25°C, (Note 3) -1 2 p F Output Capacitance C OUT -1 2 p F NOTES: 3. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 4. Power Supply current is proportional to operating frequency. Typical rating for I CCOP is 11mA/MHz. 5. Output load per test load circuit and CL = 40pF. 6. Maximum junction temperature must be consider ed when operating part at high clock frequencies. HSP43168
22 FN2808.12 July 27, 2009 AC Test Load Circuit PARAMETER SYMBOL NOTES UNITS MIN (Note 11) MAX (Note 11) MIN (Note 11) MAX (Note 11) MIN (Note 11) MAX (Note 11) CLK Period t CP 30 - 24.5 - 22 - ns CLK High t CH 12 - 10 - 8 - ns CLK Low t CL 12 - 10 - 8 - ns WR Period t WP 30 - 24.5 - 22 - ns WR High t WH 12 - 10 - 10 - ns WR Low t WL 12 - 10 - 10 - ns Setup Time A0-8 to WR Going Low t AWS 10 - 8 - 8 - ns Hold Time A0-8 from WR Going High t AWH 0-0-0- n s Setup Time CIN0-9 to WR Going High t CWS 12 - 11 - 10 - ns Hold Time CIN0-9 from WR Going High t CWH 1-1-1- n s Setup Time WR Low to CLK Low t WLCL (Note 8) 5 - 4 - 3 - ns Setup Time CIN0-9 to CLK Low t CVCL (Note 8) 7 - 7 - 7 - ns Setup Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High t ECS 15 - 13 - 12 - ns Hold Time CSEL0-5, SHFTEN, FWRD, RVRS, TXFR, INA0-9, INB0-9, ACCEN, MUX0-1 to CLK Going High t ECH 0-0-0- n s CLK to Output Delay OUT0-27 t DO -1 4-1 3-1 2 n s Output Enable Time t OE -1 2-1 2-1 2 n s Output Disable Time t OD (Note 9) - 12 - 12 - 12 ns Output Rise, Fall Time t RF (Note 9) - 6 - 6 - 6 ns NOTES: 7. AC tests performed with C L = 40pF, IOL = 2mA, and IOH = -400µA. Input reference level CLK = 2.0V. Input reference level for all other inputs is 8. Setup time requirement for loading of data on CIN0 -9 to guarantee recognition on the following clock. 9. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP Note: Test head capacitance. HSP43168
24 FN2808.12 July 27, 2009 HSP43168 Metric Plastic Quad Flatpack Packages (MQFP) D E E1 -A- PIN 1 A2 A1 A 12o-16o 12o-16o 0o-7o 0.40
0.016 MIN
L 0o MIN PLANE b 0.005/0.009 0.13/0.23WITH PLATING BASE METAL SEATING 0.005/0.007 0.13/0.17 -B- e 0.008
0.20 A-B SD SCM
0.076 0.003 -C- -D- -H- Q100.14x20 (JEDEC MS-022GC-1 ISSUE B)
100 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
A- 0.134 - 3.40 - A1 0.010 - 0.25 -- A2 0.101 0.113 2.57 2.87 - b 0.009 0.015 0.22 0.38 6 b1 0.009 0.013 0.22 0.33 - D 0.908 0.918 23.08 23.32 3 D1 0.782 0.792 19.88 20.12 4, 5 E 0.673 0.681 17.10 17.30 3 E1 0.547 0.555 13.90 14.10 4, 5 L 0.029 0.040 0.73 1.03 - N 100 100 7 e 0.026 BSC 0.65 BSC - ND 30 30 - NE 20 20 - Rev. 1 4/99 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 2. All dimensions and toleranc es per ANSI Y14.5M-1982. 3. Dimensions D and E to be determined at seating plane . 4. Dimensions D1 and E1 to be determined at datum plane 5. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm (0.010 inch) per side. 6. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total. 7. “N” is the number of terminal positions. -C- -H-
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2808.12 July 27, 2009 HSP43168 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0 .25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N84.1.15 (JEDEC MS-018AF ISSUE A)
84 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE
A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 1.185 1.195 30.10 30.35 - D1 1.150 1.158 29.21 29.41 3 D2 0.541 0.569 13.75 14.45 4, 5 E 1.185 1.195 30.10 30.35 - E1 1.150 1.158 29.21 29.41 3 E2 0.541 0.569 13.75 14.45 4, 5 N8 4 8 4 6 Rev. 2 11/97