HSP43124 RENESAS | Alldatasheet

Document overview

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  • PDF pages: 18

Technical content

Features

  • 45MHz Clock Rate
  • 256 Tap Programmable FIR Filter
  • 24-Bit Data, 32-Bit Coefficients
  • Cascade of up to 5 Half Band Filters
  • Decimation from 1 to 256
  • Two Pin Interface for Down Conversion by F S/4
  • Multiplier for Mixing or Scaling Input with an External Source
  • Serial I/O Compatible with Most DSP Microprocessors
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Low Cost FIR Filter
  • Filter Co-Processor
  • Digital Tuner Block Diagram

Ordering Information

TEMP . RANGE (°C) PACKAGE PKG. NO. HSP43124SC-45 HSP43124SC-45 0 to +70 28 Ld SOIC (300 mil) M28.3 HSP43124SC-45Z (Note) HSP43124SC-45Z 0 to +70 28 Ld SOIC (300 mil, Pb-free) M28.3 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PROGRAMMABLE FIR FILTER INPUT FORMATTER DIN SCLK SYNCIN MXIN SYNCMX OUTPUT FORMATTER DOUT SYNCOUT CLKOUT A0-2 C0-7 WR CONTROL INTERFACE RD FSYNC FCLK HALF BAND FILTER HALF BAND FILTER HALF BAND FILTER NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

FN3555 Rev 7.00 Page 2 of 18 April 18, 2007 Pinout HSP43124 (28 LD PDIP, SOIC) TOP VIEW SCLK SYNCIN GND FSYNC VCC FCLK WR RD V CC DIN SYNCOUT CLKOUT VCC GND DOUT SYNCMX MXIN

FN3555 Rev 7.00 Page 3 of 18 April 18, 2007 Pin Description NAME TYPE DESCRIPTION VCC - +5V Power Supply GND - Ground DIN I Serial Data Input. The bit value present on this input is s ampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con- tained in the Data Input Section. SYNCIN I Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYNCIN “HIGH” one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a “HIGH” state for longer than one SCLK cycle. SCLK I Serial Input CLK. The rising edge of SCLK clocks data on D IN and MXIN into the part. The following signals are synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX. MXIN I Mix Factor Input. MXIN is the serial input for the mix fac tor. It is sampled on the rising edge of SCLK. A “HIGH” on this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM output as a part of the two pin FS/4 down conversion interface. Details on word format and operation are contained in the Mix Factor Section. SYNCMX I Mix Factor Sync. The HSP43124 is synchronized to the beg inning of a serially input mix factor when SCLK samples SYNCMX “HIGH” one SCLK before the first bit of the new mix factor. NOTE: SYNCMX should only pulse “HIGH” for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin FS/4 down conversion interface. FCLK I Filter Clock. The filter clock determines the processing s peed of the Filter Compute Engine. Clock rate require- ments on FCLK for particular fil ter configurations is discussed in the Filter Compute Engine Section. This clock may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock. FSYNC I Filter Sync. This input, when sampled low by the rising edge o f FCLK, resets the filter compute engine so that the data sample following the next SYNCIN cycle is the first data s ample into the filter structure. If a data stream is currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until the next SYNCIN cycle occurs. WR I Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by the address on A0-2. The WR signal is asynchronous to all other clocks. NOTE: WR should not be low when RD is low. RD I Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus. The RD pin is asynchronous t o all other clocks. NOTE: RD should not be low when WR is low. A0-2 I Address Bus. The A0-2 inputs are decoded on the falling ed ge of both RD and WR. Table 1 shows the address map for the control registers. C0-7 I/O Control and Coefficient bus . This bidirectional bus is used to access the control registers and coefficient RAM. CLKOUT O Output Clock. Programmable bit clock for serial output. NOTE: Assertion of FSYNC initializes CLKOUT to a high state. SYNCOUT O Output Data Sync. SYNYOUT is asserted HIGH for one CLKO UT cycle before the first bit of a new output sample is available on DOUT. DOUT O Serial Data Output. The bit stream is synchronous to the r ising edge of CLKOUT. (See the Serial Output Formatter section for additional details.)

filter. The register bank consists of 128 thirty-two-bit registers. (LSB) to most significant byte (MSB). TABLE 1. CONFIGURATION CONTROL REGISTER FUNCTIONAL DESCRIPTION HBF must be enabled to get an output). 7-5 FIR Decimation Rate. Range is 1-8 (8 = 000). tual number of coefficients. side the range of 8 - 24 are invalid. 5 Number System. 0 = Two’s Complement, 1 = Offset Binary. 6 Serial Format. 1 = MSB First, 0 = LSB First. 5 1 = MSB First, 0 = LSB First. by 00000, and values from 1 to 7 are invalid. 5 Round Select. 1 = Round to Select ed Number of Bits, 0 = Truncate. 6 Number System. 0 = Two’s Complement, 1 = Offset Binary. 7 Gain Correction. 1 = Apply scale factor of 2 to data. 0 = No S caling.

110 Filter Symmetry 1-0 00 = Even Symmetric FIR Coefficients

the range of 8 - 24 are invalid. 5 Serial Format. 1 = MSB First, 0 = LSB First. 6 Mix Factor Select. 1 = Seria l Input, 0 = Weaver modulator look-up-table.

7 Unused

significant bits of the Input Holding Register are zeroed. tying both SYNCMX and MXIN “high”. register are transferred into the Mix Factor Holding Register. the Register File on the next rising edge of FCLK. NOTE: Assumes data is being loaded LSB first. FIGURE 7. SERIAL INPUT TIMING FOR EITHER DIN OR MXIN TABLE 2. WEAVER MODULATOR ROM DECODING

FN3555 Rev 7.00 Page 9 of 18 April 18, 2007 FIGURE 10A. BLOCK DIAGRAM OF FIXED COEFFICIENT HALFBAND FILTERS BITS2-0 100 0 1 11 1 101 1 1 11 1 010 0 0 01 1 011 0 0 11 1 000 0 0 00 0 001 0 0 00 1 MUX1 = (BIT2 AND BIT0) AND BIT1 MUX2 = BIT2 MUX3 = (BIT1 AND BIT0) OR BIT2 MUX4 = BIT1 OR BIT2 MUX5 = BIT0 OR BIT1 OR BIT2 INVALID = BIT2 AND BIT1 MULTIPLEXERS’ DECODER TABLE AND EQUATIONS MUX5MUX4MUX3MUX2MUX1 HB5 HB4 HB3 HB2 HB1 INPUT TO FNORMALIZED = Fs Fs FHB1= Fs or Fs/2 Fs/2 FHB1/2 FHB2 = FHB1 or FHB1/2 FNORMALIZED = FHB1 FHB3 = FHB2 or FHB2/2 FHB2/2 FNORMALIZED = FHB2 FHB3/2 FNORMALIZED = FHB3 FHB4 = FHB3 or FHB3/2 FHB4/2 FNORMALIZED = FHB4 OUTPUT OF HALFBAND SECTION HALFBAND SECTION 01MUX5 MUX4 MUX3 MUX2 MUX1

35 TAP

23 TAP

19 TAP

11 TAP

7 TAP

FIGURE 10B. SPECTRAL COMPOSITION OF FIVE CASCADED HALFBANDS FIGURE 10C. COMPOSITE RESPONSE OF FIXED COEFFI- CIENT HALFBAND FILTERS WITH RESPECT TO THE NORMALIZED FREQUENCY SHOWN IN FIG- URE 10A FCLK FCLK 3FCLK FCLK FCLK FCLK FS FS FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK FCLK STAGE 1 STAGE 2 STAGE 3 STAGE 4 STAGE 5 POSITE FILTER FCLK COM- -120 -140 -160 -180 -200 0.125 0.25 0.375 0.5 MAGNITUDE (dB) -60 -40 -20 -80 -100 6dB BANDWIDTH HB1 TRANSITION BW NORMALIZED FREQUENCY HB2 HB3 HB4 HB5 (NORMALIZED TO OUTPUT FREQUENCY)

Table 4. These values are the 32-bit, two’s complement, integer achieve unity gain in the Filter Processor. tap per multiply accumulate cycle is calculated. 256 input sample periods may be available for filter calculation. Thus, the Min FCLK is 19.6MHz. the FCLK rate must exceed 14FS. TAPS. The resulting expression is given below. by two in order to determine the correct FCLK. TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS

TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)

TABLE 4. HALFBAND FILTER COEFFICIENTS (32 BITS, UN-NORMALIZED) TABLE 3. FREQUENCY RESPONSE OF HALFBAND FILTERS (Continued)

FN3555 Rev 7.00 Page 15 of 18 April 18, 2007 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) JA (oC/W) (SOIC - Lead Tips Only) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS Power Supply Current I CCOP VCC = Max, FCLK = SCLK = 45MHz Notes 2, 3 - 203 mA Standby Power Supply Current I CCSB VCC = Max, Outputs Not Loaded - 500 A Input Leakage Current I I VCC = Max, Input = 0V or VCC -10 10 A Output Leakage Current I O VCC = Max, Input = 0V or VCC -10 10 A Clock Input High V IHC VCC = Max, FCLK and SCLK 3.0 - V Clock Input Low V ILC VCC = Min, FCLK and SCLK - 0.8 V Logical One Input Voltage V IH VCC = Max 2.0 - V Logical Zero Input Voltage V IL VCC = Min - 0.8 V Logical One Output Voltage V OH IOH = -5mA, VCC = Min 2.6 - V Logical Zero Output Voltage V OL IOL = 5mA, VCC = Min - 0.4 V Input Capacitance C IN FCLK = SCLK = 1MHz All Measurements Referenced to GND. T A = 25oC, Note 4 -1 0 p F Output Capacitance C OUT -1 0 p F NOTES: 2. Power supply current is proportional to frequency. Typical rating is 4.5mA/MHz. 3. Output load per test circuit and CL = 40pF. 4. Not tested, but characterized at initial design and at major process/design changes.

FN3555 Rev 7.00 Page 16 of 18 April 18, 2007 AC Test Load Circuit VCC = +4.75V to +5.25V, TA = -40oC to 85oC (Industrial) PARAMETER SYMBOL NOTES 45MHz 40MHz 33MHz UNITSMIN MAX MIN MAX MIN MAX FCLK, SCLK Period t CP 22 - 25 - 30 - ns FCLK, SCLK High t CH 8 - 10 - 12 - ns FCLK, SCLK Low t CL 8 - 10 - 12 - ns Setup Time DIN, MXIN, SYNCIN, SYNCMX to SCLK tDS 8-8-9-n s Hold Time DIN, MXIN, SYNCIN, SYNCMX from SCLK tDH 0-0-0-n s Setup Time FSYNC to FCLK t SS 8-8-8-n s Hold Time FSYNC from FCLK t SH 0-0-0-n s Setup Time C0-7, A0-2 to Falling Edge of WR tWS 10 - 10 - 10 - ns Hold Time C0-7, A0-2 from Falling Edge of WR tWH 3-3-3-n s Setup Time A0-2 to Falling Edge of RD tRS 10 - 10 - 10 - ns Hold Time A0-2 from Rising Edge of RD tRH 0-0-0-n s WR High t WRH 10 - 10 - 12 - ns WR Low t WRL 10 - 10 - 12 - ns RD High t RDH 10 - 10 - 10 - ns RD Low to Data Valid t RDO -2 5-2 5-2 5 n s RD High to Output Disable t OD -6-6-6 n s FCLK to CLKOUT t FOC -1 2-1 3-1 4 n s CLKOUT to SYNCOUT, DOUT t DO -8-9- 1 0 n s Output Rise, Fall Time t RF N o t e 6 -3-3-3 n s NOTES: VIH = 3.0V, VIHC = 4.0V, VIL = 0V. 6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or changes. EQUIVALENT CIRCUIT CL (NOTE) IOH 1.5V I OL DUT SWITCH S1 OPEN FOR ICCSB AND ICCOP NOTE: Test head capacitance.

FN3555 Rev 7.00 Page 18 of 18 April 18, 2007 HSP43124 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999-2007. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Small Outline Plastic Packages (SOIC) NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. In- terlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45o C H 0.25(0.010) BM M M28.3 (JEDEC MS-013-AE ISSUE C)

28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e 0.05 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N2 8 2 8 7  0o 8o 0o 8o - Rev. 0 12/93