HSP-EVAL INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Single HSP-EVAL May be Used to Evaluate a Variety of Parts Within the HSPXXXXX Family of DSP Products
- May be Daisy Chained to Support Evaluation of Multi-Chip Solutions
- Parallel Port Interface to Support IBM PC™ Based Evaluation and Control
- Three Clocking Modes for Flexibility in Performance Analysis and Prototyping
- Dual 96-Pin Input/Output Connectors Conforming to the VME J2/P2 Connector Standard
Applications
- PC Based Performance Analysis of HSPXXXXX Family of DSP Products
- Rapid Prototyping DSP Evaluation Platform USER’S MANUAL May 1999
with data through the Parallel Port Bus. Parallel Port Bus (see Configuration Jumper Field Section). data via the Parallel Port Bus. serialized by the On Board Shift Register.
96 PIN OUTPUT CONNECTOR (P2)
26 PIN HEADER
96 PIN INPUT CONNECTOR (P1)
FIGURE 1. BLOCK DIAGRAM OF HSP-EVAL
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 1. PIN ASSIGNMENTS FOR 96 PIN INPUT
1 AUXIN0 V CC GND
2 IN2_0 GND IN2_1
12 IN1_1 GND IN1_2
13 IN1_3 V
31 PCWR1 GND PCRD0
32 PCRD1 V
TABLE 2. PIN ASSIGNMENTS FOR 96 PIN OUTPUT
1 AUXOUT0 V CC GND
2 OUT2_0 GND OUT2_1
12 OUT1_1 GND OUT1_2
13 OUT1_3 V
22 GND GND STAT1
has been connected to a host PC. described in the following sections. TABLE 3. SIGNAL ASSIGNMENTS FOR 50 POSITION INPUT
1 AUX_IN0 GND
2 IN2_0 IN2_1
3 IN2_2 IN2_3
4 IN2_4 IN2_5
5 IN2_6 IN2_7
6 GND IN2_8
7 IN2_9 IN2_10
8 IN2_11 IN2_12
9 IN2_13 IN2_14
10 IN2_15 GND
11 AUX_IN1 IN1_0
12 IN1_1 IN1_2
13 IN1_3 IN1_4
14 IN1_5 IN1_6
15 IN1_7 GND
16 IN1_8 IN1_9
17 IN1_10 IN1_11
18 IN1_12 IN1_13
19 IN1_14 IN1_15
20 GND CLKIN
22 GND V
23 GND V CC
24 GND V CC
25 GND V CC
TABLE 4. SIGNAL ASSIGNMENTS FOR 50 POSITION
1 AUXOUT0 GND
2 OUT2_0 OUT2_1
3 OUT2_2 OUT2_3
4 OUT2_4 OUT2_5
5 OUT2_6 OUT2_7
6 GND OUT2_8
7 OUT2_9 OUT2_10
8 OUT2_11 OUT2_12
9 OUT2_13 OUT2_14
10 OUT2_15 GND
11 AUXOUT1 OUT1_0
12 OUT1_1 OUT1_2
13 OUT1_3 OUT1_4
14 OUT1_5 OUT1_6
15 OUT1_7 GND
16 OUT1_8 OUT1_9
17 OUT1_10 OUT1_11
18 OUT1_12 OUT1_13
19 OUT1_14 OUT1_15
20 GND CLKOUT
21 GND STAT0
22 GND STAT1
23 GND STAT2
24 GND STAT3
by a 32-bit shift register for reading via the Parallel Port Bus. to the output busses is shown in Table 8. mentioned above to the PC's parallel port is given in Table 6. TABLE 5. SIGNAL ASSIGNMENTS FOR 50 POSITION
2 IN3_0 IN3_1
3 IN3_2 IN3_3
4 IN3_4 IN3_5
5 IN3_6 IN3_7
6 GND IN3_8
7 IN3_9 IN3_10
8 IN3_11 IN3_12
9 IN3_13 IN3_14
10 IN3_15 GND
12 CTL1 CTL2
13 CTL3 CTL4
14 CTL5 CTL6
15 CTL7 GND
16 CTL8 CTL9
17 CTL10 CTL11
18 CTL12 CTL13
19 CTL14 CTL15
TABLE 6. SIGNAL MAPPING SFOR 27 PIN SHROUDED
3 PCD1 (D1) PCWR0 (INIT
4 PCD2 (D2) PCWR1 (SELECT
5 PCD3 (D3) GND
6 PCD4 (D4) GND
7 PCD5 (D5) GND
8 PCD6 (D6) GND
9 PCD7 (D7) GND
11 PCRD0 (BUSY) GND
12 PCRD2 (PAPER
13 PCRD1 (SELECT) GND
bit position (see Table 9 for Address Register Bit Map). into the target data register on the specified HSP-EVAL. STAT0-3 positions of the J4 Jumper Configuration Field. TABLE 7. SHIFT REGISTER TO OUTPUT BUS MAPPINGS TABLE 8. ADDRESS REGISTER BIT MAP TABLE 9. REGISTER TO INPUT/CONTROL BUS MAPPINGS
output of the respective register is three-stated. respectively. Only one jumper may be inserted in this field. then selecting the desired Parallel Port Bus serial output line. inserting a jumper in the SR_RD position. Intersil or Intersil’s' authorized representatives. possibility of such damages. with, such revisions or changes. FIGURE 4. CONFIGURATION JUMPER FIELD J4
OE_BUS1 U11 R SIP10 VCC 2 1 OE_BUS2 OE_BUS3 74AC138 IN2_[0..15] U9U2 RNGSEL PCWR0 A B C G1 6 G2A4 G2B5 Y0 15 Y1 14 Y2 13 Y3 12 Y4 11 Y5 10 Y6 9 Y7 7 U12 74AC138 U3 U10 IN3_[0..15] 74AC574PCD[0...7] PCWR1 IN1_[0..15] ADRNG[0..7] CTL[0..15] D[0..7] ADRNG[0..7] OECTLLO VCC GND VCC R SIP10 74AC574 PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 12 1 ADRNG0 ADRNG1 ADRNG2 ADRNG3 ADRNG4 ADRNG5 ADRNG6 ADRNG7 PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 PCD0 PCD7 PCD6 PCD5 PCD4 PCD3 PCD2 PCD1 VCC D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 CTL8 CTL9 CTL10 CTL11 CTL12 CTL13 CTL14 CTL15 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 CTL0 CTL1 CTL2 CTL3 CTL4 CTL5 CTL6 CTL7 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 INT_0 IN3_2 IN3_3 IN3_4 IN3_5 IN3_6 IN3_7 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 IN2_0 IN2_1 IN2_2 IN2_3 IN2_4 IN2_5 IN2_6 IN2_7 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 IN2_8 IN2_9 IN2_10 IN2_11 IN2_12 IN2_13 IN2_14 IN2_15 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 IN1_0 IN1_1 IN1_2 IN1_3 IN1_4 IN1_5 IN1_6 IN1_7 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC 74AC574 PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 IN1_8 IN1_9 IN1_10 IN1_11 IN1_12 IN1_13 IN1_14 IN1_15 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8 CLK OC A B C G2A G2B OECTLHI IN3_1 IN3_8 IN3_10 IN3_11 IN3_12 IN3_13 IN3_14 IN3_15 IN3_9 PAGE 1 OF 4 HSP-EVAL
P R C U17B 74AC74 L 74HCT165 ST CTL1 STAT[0..3] SER A B C D E F G H QH 9 CLK QH 7INH SH/LD U13 OUT1_0 OUT1_1 OUT1_2 OUT1_3 OUT1_4 OUT1_5 2 1 D 2 Q 5 CLK 3 Q 6 P R C U17A 74AC74 STRD OUT1_6 OUT1_7 ST1 OSCOUT OUT U18 OSC ST2 OUT1_[0..15] OUT1_[0..15] OUT2_8 OUT2_9 OUT2_10 OUT2_11 OUT2_12 VCC GND VCC ST3 OUT2_13 OUT2_14 OUT2_15 CTL2 CTL3 OUT2_[0..15] SRRD ST0 OUT1_8 OUT1_9 OUT1_10 OUT1_11 OUT1_12 OUT1_13 OUT1_14 OUT1_15 OUT2_0 OUT2_1 OUT2_2 OUT2_3 OUT2_4 OUT2_5 OUT2_6 OUT2_7 OUT1_0 OUT1_1 OUT1_2 OUT1_3 OUT1_4 OUT1_5 OUT1_6 OUT1_7 74HCT165 SER A B C D E F G H QH 9 CLK QH 7INH SH/LD U14 OUT1_8 OUT1_9 OUT1_10 OUT1_11 OUT1_12 OUT1_13 OUT1_14 OUT1_15 74HCT165 SER A B C D E F G H QH 9 CLK QH 7INH SH/LD U15 OUT2_0 OUT2_1 OUT2_2 OUT2_3 OUT2_4 OUT2_5 OUT2_6 OUT2_7 74HCT165 SER A B C D E F G H QH 9 CLK QH 7INH SH/LD U16 OUT2_8 OUT2_9 OUT2_10 OUT2_11 OUT2_12 OUT2_13 OUT2_14 OUT2_15 PAGE 2 OF 4 L HSP-EVAL
OUT2_4 OUT2_0 OUT2_2 P2C VCC OUT2_1 OUT2_3 OUT2_5 P1A P1B VCC P1C IN1_9 IN1_11 IN1_13 IN1_15 IN1_1 IN1_3 IN1_5 IN1_7 IN1_8 IN1_10 IN1_12 IN1_14 OUT1_0 OUT1_2 OUT1_4 OUT1_6 OUT1_9 OUT1_11 OUT1_13 OUT1_15 OUT2_7 OUT2_8 OUT2_10 OUT2_12 OUT2_14 OUT1_1 OUT1_3 OUT1_5 OUT1_7 OUT1_8 OUT1_10 OUT1_12 OUT1_14 OUT2_6 OUT2_9 OUT2_11 OUT2_15 OUT2_13 PCRD1 PCD0 PCD2 PCD4 PCD6 PCRD0 PCRD2 PCD1 PCD3 PCD5 PCD7 STAT0 STAT1 STAT2 STAT3 PCRD1 PCRD0 PCRD2 PCRD[0..2] PCD[0..7] IN2_[0..15] IN1_[0..15] OUT1_[0..15] OUT2_[0..15] STAT[0..3] PCWR0 PCWR1 CLKIN CONN VCC VCC GND IN2_1 IN2_3 IN2_5 IN2_7 IN2_8 IN2_10 IN2_12 IN2_14 IN1_0 IN1_2 IN1_4 IN1_6 PCD0 PCD2 PCD4 PCD6 IN2_0 IN2_2 IN2_4 IN2_6 IN2_9 IN2_11 IN2_13 IN2_15 PCD1 PCD3 PCD5 PCD7 PAGE 3 OF 4 HSP-EVAL
OUT1_7 10µF CLKOUT AUXIN0 AUXOUT1 AUXOUT0 1 J1A IN2_6 J1B J2A J2B VCC AUXIN1 C15 0.1µF 0.1µF 0.1µF C16 0.1µF C17 0.1µF C18 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF C10 0.1µF C14 0.1µF C13 0.1µF C11 0.1µF C12 0.1µF STATO OUT1_0 OUT1_2 OUT1_4 OUT1_6 OUT1_9 OUT1_11 OUT1_13 OUT1_15 STAT1 STAT2 STAT3 OUT1_8 CLK IN1_0 IN1_2 IN1_4 IN1_6 IN1_9 IN1_11 IN1_13 IN1_15 CTL[0..15] IN1_[0..15] IN2_[0..15] VCC OUT1_[0..15] OUT2_[0..15] PCWR1 PCWR0 J5B J5A CLK CTL0 OSCOUT CLKIN OEBUS1 OEBUS2 OEBUS3 J3B CTL0 J3AOSCOUT IN3_[0..15] CLKIN CTL1 CTL3 CTL5 CTL7 CTL8 CTL10 CTL12 CTL14 IN3_9 IN3_11 IN3_13 IN3_15 ADRNG0 ADRNG1 ADRNG2 ADRNG3 ADRNG4 ADRNG5 ADRNG6 ADRNG7 PCRD1 PCRD0 STAT0 STAT1 STAT2 STAT3 OECTLLO OECTLHI PCRD0 PCRD2 PCRD1 PCD[0..7] STAT[0..3] PCRD2 VCCADRNG[0..7] VCC GND GND STRD SRRD PCRD[0..2] IN3_0 IN3_2 IN3_4 IN3_6 IN3_1 IN3_3 IN3_5 IN3_7 IN3_8 CTL0 CTL2 CTL4 CTL6 CTL9 CTL11 CTL13 CTL15 IN3_10 IN3_12 IN3_14 IN2_0 IN2_2 IN2_4 IN2_9 IN2_11 IN2_13 IN2_15 IN1_1 IN1_3 IN1_5 IN1_7 IN1_8 IN1_10 IN1_14 IN1_12 IN2_1 IN2_3 IN2_5 IN2_7 IN2_8 IN2_10 IN2_12 IN2_14 OUT2_4 OUT2_0 OUT2_2 OUT2_6 OUT2_9 OUT2_11 OUT2_13 OUT2_15 OUT1_1 OUT1_3 OUT1_5 OUT1_10 OUT1_12 OUT1_14 OUT2_1 OUT2_3 OUT2_5 OUT2_7 OUT2_8 OUT2_10 OUT2_12 OUT2_14 OEBUS1 RNGSEL OEBUS2 OEBUS3 ST OECTLLO OECTLHI PCD0 PCD1 PCD2 PCD3 PCD4 PCD5 PCD6 PCD7 PAGE 4 OF 4 HSP-EVAL