HSDL-7000

HSDL-7000 HP | Alldatasheet

Document overview

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Technical content

Features

• Compliant with IrDA Physical Layer Specs
• Interfaces with IrDA Compliant HSDL-1000 IR Transceiver
• 1 Micron CMOS Gate Array
• Used in Conjunction with Standard 16550 UART
• Pin Compatible with PLX-1000

Applications

HSDL-1000 to perform:

• Serial Half-Duplex Data Transfer Between: Notebook Computers Subnotebooks Desktops PCs PDAs Printers Other Peripheral Devices
• Telecom Applications in: Modems Fax Machines Pagers Phones
• Industrial Applications in: Data Collection Devices
• Medical Applications in: Patient and Pharmaceutical Data Collection

Description

The HSDL-7000 performs the modulation/demodulation function used to both encode and decode the electrical pulses from the IR transceiver. These pulses are then sent to a standard UART which has a BAUDOUT signal available externally. This signal is 16 times the selected baud rate. In applications where the 16XCLK is not available, an external means of generating the 16XCLK must be designed. The HSDL-7000 is comprised of two state machines – the serial IR encode and the serial IR decode blocks. Each of these blocks derives their timing from the 16XCLK input signal from the UART. The Encode block is driven by the negative edge triggered TXD signal from the UART. This initiates the modula- tion state machine resulting in the 3/16 modulated IR_TXD signal which drives the IR trans- ceiver module, HSDL-1000. The IR Decode block is driven by the negative edge triggered IR_RCV signal from the HSDL-1000. After this signal is demodulated and stretched, it drives the RCV signal to the UART. Schematic HSDL-7000 IR ENCODE IR DECODE TXD IR_TXD RCV IR_RCV NRST Pin Out 116XCLK 2TXD 3RCV 4GND

8 VCC

7 IR_TXD

6 IR_RCV

5 NRST

triggered input clock that is set to 16 times the data transmission baud rate. The encode and decode schemes require this signal. The signal is usually tied to a UART’s BAUDOUT signal. TXD - Negative edge triggered input signal; usually tied to a UART’s SOUT signal (serial data to be transmitted). RCV - Output signal which is usually tied to a UART’s SIN signal (received serial data). GND - Chip ground. NRST - Active low signal used to reset the decode state machine. This signal can be tied to POR (Power on reset) or V CC. This signal can also be used to disable any data reception. IR_RCV - A 3/16th pulse width input signal from the HSDL-1000. The signal is a demodulated (pulse stretched) to generate the RCV output signal. IR_TXD - This signal is the modulated 3/16ths TXD signal which is input to the HSDL-1000. V CC - Power. Package Dimensions 7.7 ± 0.3 (0.30 ± 0.012) 0.15 + 0.10/-0.00 SEE DETAIL A 5.60 (0.22) 6.65 (0.26) MAX. 0.40 + 0.10/-0.00 1.55 (0.06) 1.42 (0.056) MAX. 1.27 (0.05) 0.6 ± 0.2 (0.024 ± 0.008) DETAIL A, SCALE 20 0.10 (0.004) 1.05 (0.041) SCALE 5 NOTE: DIMENSIONS IN MILLIMETERS (INCHES).

16 X CLOCK

16 CLOCK CYCLES

The encoder sends a pulse for every space or “0” that is sent on the TXD line. On a high to low transition of the TXD line, the generation of the pulse is delayed for 7 clock cycles of the 16XCLK before the pulse is set high for 3 clock cycles (or 3/16th of a bit time) and then subsequently pulled low. A high to low transition of the IR_RXD line from the HSDL-1000 signifies a 3/16th pulse. This pulse is stretched to accommo- date 1 bit time (16 clock cycles). Every pulse that is received is translated into a “0” or space on the RXD line equal to 1 bit time. Note: The stretched pulse must be at least 3/4 of a bit time in duration to be correctly interpreted by a UART. IR_RXD RXD 3 cs

(VCC = 0 Volts, TA= -40 to +85°C) Parameter Symbol Min. Typ. Max. Units Conditions Input Capacitance C IN 10 20 pF f = 1 MHz - Unmeasured Pins Output Capacitance C OUT 10 20 pF Output Fall Time 10 20 pF Returned to 0 Volts Absolute Maximum Ratings Parameter Symbol Min. Max. Units Conditions Storage Temperature T S -65 +150 °C Operating Temperature T A -40 +85 °C Output Current I O 10 mA Power Dissipation P MAX 0.22 W Input/Output Voltage V I/VO -0.5 V CC + 0.5 V Power Supply Voltage V CC -0.5 +6.5 V Switching Specifications (VCC = 5 Volts ± 10%, TA= -40 to +85°C) Parameter Symbol Min. Typ. Max. Units Conditions Toggle Frequency f tog 120 Mhz Propagation Delay Time t pd 0.5 ns Internal Gate 1.0 ns Input Buffer 2.0 ns Output Buffer Output Fall Time t f 1.42 ns Output Buffer (C L = 15 pF) Output Rise Time t r 1.54 ns Output Buffer (C L = 15 pF) Note: ftog represents the maximum internal D-Type Flip Flop toggle rate

Recommended Operating Conditions (TA= -40 to +85°C) Parameter Symbol Min. Typ. Max. Units Conditions Supply Voltage V CC 2.7 5.0 5.5 V CMOS level Input Voltage V I 0.0 V CC V CMOS level Ambient Temperature T A -40 +85 °C CMOS level High Level Input Voltage V IH 0.7 VCC VCC V CMOS level Low Level Input Voltage V IL 0.0 0.3 V CC V CMOS level Positive Trigger Voltage V P 1.61 4.00 V CMOS level Negative Trigger Voltage V N 0.55 3.10 V CMOS level Hysteresis Voltage V H 0.50 2.00 V CMOS level Power Dissipation P DISS 4.9 220 mW f 16XCLK = 2 MHz Input Rise Time t ri 200 ns f 16XCLK = 2 MHz Input Fall Time t fa 200 ns f 16XCLK = 2 MHz Max Clk Frequency (16XCLK) f 16XCLK 2 MHz Minimum Pulse Width (IR_TXD)* t mpx 250 ns f 16XCLK = 2 MHz *IrDA Parameters. The Max Clk Frequency represents the maximum clock frequency to drive the HSDL-7000’s internal state machine. Under normal circumstances, this clock input should not exceed 16 * 115.2 Kbp/s or 1.8432 MHz. This product can operate at higher clock rates, but the above is the recommended rate. The Minimum Pulse Width represents the minimum pulse width of the encoded IR_TXD pulse (and the IR_RCV pulse). As per the IrDA specifications, the minimum pulse width of the IR_TXD and IR_RCV pulses should be 3 * (1/1.8432 MHz) or 1.63 µs. The minimum pulse width specified for the HSDL-7000 is 250 ns, which is within IrDA specification. Under normal circumstances, the pulse width should not be less than 1.63 µs. Application Circuits HSDL-7000 Connection to UART TXD HSDL-1000 HSDL-7000 RCV IR_TXD IR_RCV SOUT BAUDOUT TXD 16XCLK RCV UART 16550 SIN Note: At the time of this publication, Light Emitting Diodes (LEDs) that are contained in this product are regulated for eye safety in Europe by the Commission for European Electrotechnical Standardization (CENELEC) EN60825-1. Please refer to Application Briefs I-008, I-009, I-015 for more information.