HSDL-3220 HP | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 19
Technical content
Part Number Packaging T ype Package Quantity HSDL-3220-021 Tape and Reel Front View 2500 HSDL-3220-001 Tape and Reel Front View 500 I/O Pins Configuration Table Pin Symbol Description I/O T ype Notes
1 LED A LED Anode I 1
2 LED C LED Cathode 2
3 TXD Transmit Data. Active High. I 3 4 RXD Receive Data. Active Low. O 4 5 SD Shutdown. Active High. I 5
6 Vcc Supply Voltage 6
7 IOVcc Input/Output ASIC Vcc 7
8 GND Ground 8
- Shield EMI Shield 9 Marking Information The unit is marked with the letter “G” and “YWWLL” on the shield where: Y is the last digit of the year WW is the work week LL is the lot information Recommended Application Circuit Components Component Recommended Value Notes R1 5.6 Ω ± 5%, 0.25 watt for 2.7 ≤Vled < 3.3V 10Ω ± 5%, 0.25 watt for 3.3 ≤Vled < 4.2V 15Ω ± 5%, 0.25 watt for 4.2 ≤Vled < 5.5V CX1, CX4 0.47 µF ± 20%, X7R Ceramic 10 CX2, CX3 6.8 µF ± 20%, T antalum 11 Notes: 1. Tied through external series resistor, R1, to regulated Vled from 2.7 to 5.5V. Please refer to table above for recommended series resistor value. 2. Internally connected to LED driver. Leave this pin unconnected. 3. This pin is used to transmit serial data when SD pin is low. If this pin is held high for longer than 50 µs, the LED is turned off. Do NOT float this pin. 4. This pin is capable of driving a standard CMOS or TTL load. No external pull-up or pull-down resistor is required. The pin is in tri-state when the transceiver is in shutdown mode. The receiver output echoes transmitted signal. 5. The transceiver is in shutdown mode if this pin is high for more than 400 µs. On falling edge of this signal, the state of the TXD pin sampled and used to set receiver low bandwidth (TXD=low) or high bandwidth (TXD=high) mode. Refer to the section ”Bandwidth selection timing” for programming information. Do NOT float this pin. 6. Regulated, 2.7 to 3.6 Volts. 7. Connect to ASIC logic controller Vcc voltage or supply voltage. The voltage at this pin must be equal to or less than supply voltage. 8. Connect to system ground. 9. Connect to system ground via a low inductance trace. For best performance, do not connect directly to the transceiver pin GND. 10. CX1 must be placed within 0.7 cm of the HSDL-3220 to obtain optimum noise immunity. 11. In environments with noisy power supplies, including CX2, as shown in Figure 1, can enhance supply ripple rejection performance. Application Support Information The Application Engineering Group is available to assist you with the application design associated with the HSDL-3220 infrared transceiver module. You can contact them through your local sales representatives for additional details.
- Set SD/Mode input to logic
- TXD input should remain at
- Ensure that TXD input re-
- SD input pulse width for mode
selection should be > 50 ns.
- Set SD/Mode input to logic
Figure 3. Bandwidth selection timing at SIR/MIR mode. Figure 4. Bandwidth selection timing at FIR mode.
- In-band IrDA signals and data rates ≤ 4.0 Mbit/s
- RXD logic low is a pulsed response. The condition is maintained for a duration dependent on pattern and strength of the inci dent intensity.
- After SD/Mode input remains
- Then set SD/Mode to logic
- SD input pulse width mode
selection should be > 50 ns.
For implementations where case to ambient thermal resistance is ≤50°C/W. Parameter Symbol Min. Max. Units Conditions Storage T emperature T S -40 +100 °C Operating Temperature T A -25 +70 °C LED Anode Voltage V LEDA 0 6.5 V Supply Voltage V CC 0 6.5 V Input Voltage: TXD, SD/Mode V I 0 6.5 V Output Voltage: RXD V O 0 6.5 V DC LED Transmit Current I LED (DC) 50 mA Average Transmit Current I LED (PK) 200 mA ≤90 µs pulse width ≤25% duty cycle Recommended Operating Conditions Parameter Symbol Min. Typ. Max. Units Conditions Supply Voltage V CC 2.7 3.6 V Input/Output Voltage IOVcc 1.8 Vcc V Logic Input Voltage Logic High V IH IOVcc – 0.5 IOV cc V for TXD, SD/Mode Logic Low V IL 0 0.4 V Logic High EIH, min 0.0081 mW/cm 2 9.6kbit/s ≤ in-band signals ≤1.152 Mbit/s[14] Receiver Input Irradiance 0.020 mW/cm 2 1.152 Mbit/s < in-band signals ≤ 4.0 Mbit/s[14] EIH, max 500 mW/cm 2 9.6 kbit/s ≤ in-band signals ≤ 4.0 Mbit/s[14] Logic Low E IL 0.3 µW/cm2 For in-band signals[14] LED (Logic High) Current I LEDA 150 mA Pulse Amplitude Receiver Data Rate 0.0096 4.0 Mbit/s Note : 14. An in-band optical signal is a pulse/sequence where the peak wavelength, λp, is defined as 850 ≤ λp ≤ 900 nm, and the pulse characteristics are compliant with the IrDA Serial Infrared Physical Layer Link Specification v1.4. CAUTIONS: The BiCMOS inherent to the design of this component increases the component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD.
Electrical and Optical Specifications Specifications (Min. and Max. values) hold over the recommended operating conditions unless otherwise noted. Unspecified test conditions may be anywhere in their operating range. All typical values (T yp.) are at 25°C, Vcc set to 3.0V and IOVcc set to 1.8V unless otherwise noted. Parameter Symbol Min. Typ. Max. Units Conditions Receiver Viewing Angle 2 θ 30 ° Peak Sensitivity Wavelength λp 880 nm RXD Output Voltage Logic High V OH IOVCC – 0.2 IOV CC VI OH = -200 µA, EI ≤ 0.3 µW/cm2 Logic Low V OL 0 0.4 V I OL = 200 µA, EI ≥ 8.1 µW/cm2 RXD Pulse Width (SIR)[15] tPW (SIR) 1 4.0 µs θ ≤ 15°, CL = 9 pF RXD Pulse Width (MIR)[16] tPW(MIR) 100 500 ns θ ≤ 15°, CL = 9 pF RXD Pulse Width (FIR) [16] tPW(FIR) 80 175 ns θ ≤ 15°, CL = 9 pF RXD Rise and Fall Times t r, tf 60 ns C L = 9 pF Receiver Latency Time[17] tL 25 50 µs Receiver Wake Up Time[18] tW 50 100 µs Transmitter Radiant Intensity IE H 10 45 mW/sr I LEDA= 150 mA, θ ≤ 15°, VTXD ≥ VIH, VSD ≤ VIL, T a=25°C Viewing Angle 2 θ 30 60 ° Peak Wavelength λp 875 nm Spectral Line Half Width ∆λ 35 nm TXD Input Current High I H 10 µAV TXD ≥ VIH Low I L 10 µA0 ≤ VTXD ≤ VIL LED ON Current I LEDA 150 mA V TXD ≥ VIH, R1=5.6ohm, Vled=3.0V TXD Pulse Width (MIR) t PW(MIR) 148 217 260 ns t PW (TXD) = 217 ns at 1.152 Mbit/s TXD Pulse Width (FIR) t PW(FIR) 115 125 135 ns t PW(TXD)=125 ns at 4.0 Mbit/s Maximum Optical PW[19] tPW(max.) 50 100 µs TXD Rise and fall Time (Optical) t r, tf 600 ns t PW(TXD) = 1.4 µs at 115.2 kbit/s 40 ns t PW (TXD) = 125 ns at 4.0 Mbit/s LED Anode On-State Voltage V ON(LEDA) 1.6 2.1 V I LEDA=150 mA, VTXD≥VIH Transceiver Supply Current Shutdown I CC1 0.1 1 µAV SD ≥ VIH, T a= 25°C Idle I CC2 1.8 3.0 mA V SD ≤ VIL, VTXD ≤ VIL, EI=0 Notes: 15. For in-band signals from 9.6 kbit/s to 115.2 kbit/s, where 9 µW/cm2 ≤ EI ≤ 500 mW/cm2. 17. Latency time is defined as the time from the last T xD light output pulse until the receiver has recovered full sensitivity. 18. Receiver wake up time is measured from Vcc power on or SD pin high to low transition to a valid RXD output. 19. The maximum optical PW is the maximum time the LED remains on when the TXD is constantly high. This is to prevent long turn on time of the LED for eye safety protection.
2.0 0.4 0.8
HSDL-3220 Tape and Reel Dimensions Note: The carrier tape is compliant to the packaging materials standards for ESD sensitive device, EIA-541 Unit: mm 1.75 ± 0.1 7.5 ± 0.1 16.0 ± 0.2 8.0 ± 0.1 8.4 ± 0.1 4.0 ± 0.1 1.5 ± 0.1 3.4 ± 0.1 Progressive Direction 2.8 ± 0.1 0.4 ± 0.05 POLARITY Ø1.5+0.1 Pin 8: VLED Pin 1: GND Empty (40 mm min) Parts Mounted Leader (400 mm min) Empty (40 mm min) Unit: mm LABEL Detail A Option # "B" 178 60 Quantity 500001 330 80 2500021 "C" 13.0 ± 0.5 2.0 ± 0.5 21 ± 0.8 R1.0 Detail A 2.0 ± 0.5 16.4 +2 BC
Figure 11. Baking conditions chart. Baking should only be done once.
Recommended Reflow Profile Process Zone Symbol ∆T Maximum ∆T/∆time Heat Up P1, R1 25 °C to 160°C4 °C/s Solder Paste Dry P2, R2 160 °C to 200°C 0.5 °C/s Solder Reflow P3, R3 200 °C to 255°C (260°C at 10 seconds max) 4 °C/s P3, R4 255 °C to 200°C- 6 °C/s Cool Down P4, R5 200 °C to 25°C- 6 °C/s The reflow profile is a straight- line representation of a nominal temperature profile for a convec- tive reflow solder process. The temperature profile is divided into four process zones, each with different ∆T/∆time temperature change rates. The ∆T/∆time rates are detailed in the above table. The temperatures are measured at the component to printed circuit board connections. In process zone P1, the PC board and HSDL-3220 castellation pins are heated to a temperature of 160°C to activate the flux in the solder paste. The temperature ramp up rate, R1, is limited to 4°C per second to allow for even heating of both the PC board and HSDL-3220 castellations. Process zone P2 should be of sufficient time duration (60 to 120 seconds) to dry the solder paste. The temperature is raised to a level just below the liquidus point of the solder, usually 200°C (392°F). Process zone P3 is the solder reflow zone. In zone P3, the temperature is quickly raised above the liquidus point of solder to 255°C (491°F) for optimum results. The dwell time above the liquidus point of solder should be between 20 and 60 seconds. It usually takes about 20 seconds to assure proper coalescing of the solder balls into liquid solder and the formation of good solder connections. Beyond a dwell time of 60 seconds, the intermetallic growth within the solder connec- tions becomes excessive, result- ing in the formation of weak and unreliable connections. The temperature is then rapidly reduced to a point below the solidus temperature of the solder, usually 200°C (392°F), to allow the solder within the connections to freeze solid. Process zone P4 is the cool down after solder freeze. The cool down rate, R5, from the liquidus point of the solder to 25°C (77°F) should not exceed 6°C per second maximum. This limitation is necessary to allow the PC board and HSDL-3220 castellations to change dimensions evenly, putting minimal stresses on the HSDL-3220 transceiver. t-TIME (SECONDS) T – TEMPERATURE – (°C) 230 200 160 120 50 150 100 200 250 30 0 180 220 255 HEAT UP SOLDER PASTE DRY SOLDER REFLOW COOL DOWN R3 R4 60 sec. MAX. ABOVE 220°C MAX. 260°C
- The ground plane should be
- The shield trace is a wide, low
which carries a high current. Figure 16. PCB layout suggestion. GROUND PIN TO BOTTOM GROUND LAYER.
- Preferably a multi-layered
Link Design Guide for details. an example of a 4 layer board.
Description
The HSDL-3220, a low-cost and small form factor infrared trans- ceiver, is designed to address the mobile computing market such as PDAs, as well as small-embedded mobile products such as digital cameras and cellular phones. It is fully compliant to IrDA 1.4 low power specification from 9.6 kbit/s to 4.0 Mbit/s, and supports HP-SIR and TV Remote modes. The design of the HSDL- 3220 also includes the following unique features:
- Low passive component count.
- Shutdown mode for low power consumption requirement.
- Interface to input/output logic circuits as low as 1.8V Selection of Resistor R1 Resistor R1 should be selected to provide the appropriate peak pulse LED current over different ranges of Vcc as shown in the table below. TRANSCEIVER MOD/ DE-MODULATOR SPEAKER RF INTERFACE AUDIO INTERFACE USER INTERFACE MICROCONTROLLER DSP CORE ASIC CONTROLLER IR MICROPHONE HSDL-3220
Figure 17. Mobile phone platform.
Figure 18. PDA platform.
Figure 19. Window design diagram. photodiode lens, K, is 5.1mm. index of the window material.
Polycarbonate is recommended. should be measured at 875 nm. effect of the front surface curve. Note: 920A and 940A are more flame retardant than 141. Figure 22. Shape of windows.
www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (916) 788-6763 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright © 2003-2005 Agilent Technologies, Inc. Obsoletes 5989-3140EN August 18, 2005 5989-3640EN