HSD8M32F4V

HSD8M32F4V HANBIT | Alldatasheet

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Technical content

REV.1.0 (August.2002) PIN ASSIGNMENT Stackable Memory Module TOP VIEW GENERAL DESCRIPTION The HSD8M32F4V/VA is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 8M x 8 bit with 4banks Synchronous DRAMs in TSOP -II packages is mounted on a 120-pin, single-sided, FR-4-printed circuit board., Two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32F4V/VA is a SMM (Stackable Memory Module) designed and is intended for mounting into two 60- pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high perform ance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• Part Identification HSD8M32F4V : Height from bottom to top 11.3mm HSD8M32F4VA : Height from bottom to top 7.3mm
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• 120pin SMM type FR4-PCB design
• The used device is 4Mx8bit x4Banks SDRAM
• Pin assignment is compatible with - HSD16M64F8V/VA - HSD32M64F8V/VA - HSD8M64F8V/VA Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) SMM based on 8Mx8, 4Banks, 4K Ref., 3.3V Part No . HSD8M32F4V/VA 60-PIN P1 Connector 60-PIN P2 Connector PIN Symbol PIN Symbol PIN Symbol PIN Symbol

1 Vcc 31 Vss 1 Vss 31 Vcc

2 DQ32 32 DQ0 2 DQ16 32 DQ48

3 DQ33 33 DQ1 3 DQ17 33 DQ49

4 DQ34 34 DQ2 4 DQ18 34 DQ50

5 DQ35 35 DQ3 5 DQ19 35 DQ51

6 DQ36 36 DQ4 6 DQ20 36 DQ52

7 DQ37 37 DQ5 7 DQ21 37 DQ53

8 DQ38 38 DQ6 8 DQ22 38 DQ54

9 DQ39 39 DQ7 9 DQ23 39 DQ55

10 Vcc 40 Vss 10 Vss 40 Vcc

11 DQ40 41 DQ8 11 DQ24 41 DQ56

12 DQ41 42 DQ9 12 DQ25 42 DQ57

13 DQ42 43 DQ10 13 DQ26 43 DQ58

14 DQ43 44 DQ11 14 DQ27 44 DQ59

15 DQ44 45 DQ12 15 DQ28 45 DQ60

16 DQ45 46 DQ13 16 DQ29 46 DQ61

17 DQ46 47 DQ14 17 DQ30 47 DQ62

18 DQ47 48 DQ15 18 DQ31 48 DQ63

19 Vcc 49 Vss 19 Vss 49 Vcc

20 DQM4 50 DQM0 20 DQM2 50 DQM6

21 DQM5 51 DQM1 21 DQM3 51 DQM7

22 NC 52 /WE 22 NC 52 NC

23 CKE0 53 CLK0 23 BA0 53 A11

24 CKE1 54 CLK1 24 BA1 54 A9

25 Vcc 55 Vss 25 A10/AP 55 A8

26 NC 56 /CAS 26 A0 56 A7

27 NC 57 /RAS 27 A1 57 A6

28 /CE2 58 /CE0 28 A2 58 A5

29 NC 59 NC 29 A3 59 A4

30 Vcc 60 Vss 30 Vss 60 Vcc

REV.1.0 (August.2002) FUNCTIONAL BLOCK DIAGRAM DQ0-31 CKE CLK CAS DQ0-7 RAS DQM0 CE WE A0 -A11 BA0 -1 U1 /CAS /CE0 /RAS /WE A0 - A11 BA0-1 CKE0 DQM0 CLK0 Two 0.01uF Capacitor per each SDRAM CKE CLK CAS DQ8-15 RAS DQM0 CE WE A0 -A11 BA0 -1 DQM1 CLK0 CKE CLK CAS DQ16-23 RAS DQM0 CE WE A0 -A11 BA0 -1 DQM2 CLK0 CKE CLK CAS DQ24-31 RAS DQM0 CE WE A0 -A11 BA0 -1 DQM3 CLK0 Vcc Vss

REV.1.0 (August.2002) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Voltage on Any Pin Relative to Vss VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 4W Storage Temperature TSTG -55oC to 150oC Short Circuit Output Current IOS 400mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

REV.1.0 (August.2002) DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Clock CCLK 2.5 1.6 pF /RAS, /CAS,/WE,/CS, CKE, DQM CIN 2.5 20.0 pF Address CADD 2.5 20.0 pF DQ (DQ0 ~ DQ7) COUT 4.0 26.0 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) VERSION PARAMETER SYMBOL TEST CONDITION -13 -12 -10 -10L UNIT NOTE Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0mA 300 300 280 280 mA 1 ICC2P CKE ≤ VIL(max) tCC=10ns 4 mA Precharge standby current in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ 4 mA Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min) CS* ≥ VIH(min), tCC=10ns Input signals are changed one time during 20ns 60 mA

REV.1.0 (August.2002) ICC2NS CKE ≥ VIH(min) CLK ≤ VIL(max), tCC=∞ Input signals are stable ICC3P CKE ≤ VIL(max), tCC=10ns 20 Active standby current in power-down mode ICC3PS CKE&CLK ≤ VIL(max) tCC=∞ mA ICC3N CKE≥VIH(min), CS*≥VIH(min), tCC=10ns Input signals are changed one time during 20ns 120 Active standby current in non power-down mode (One bank active) ICC3NS CKE≥VIH(min) CLK ≤VIL(max), tCC=∞ Input signals are stable mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 600 580 500 500 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 880 880 840 840 mA 2 4 mA Self refresh current ICC6 CKE ≤ 0.2V 3200 mA Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT AC Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 Ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2

REV.1.0 (August.2002) OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) 100 ns Row cycle time tRC(min) 65 68 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + 20 ns Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. +3.3V 1200Ω 870Ω 50pF* DOUT Vtt=1.4V 50Ω 50pF DOUT Z0=50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

REV.1.0 (August.2002) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 -12 -10 -10L PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT NOTE CAS latency=3 7.5 8 10 10 CLK cycle time CAS latency=2 tCC 1000 1000 1000 1000 ns 1 CAS latency=3 5.4 6 6 6 CLK to valid output delay CAS latency=2 tSAC - - 6 7 ns 1,2 CAS latency=3 2.7 3 3 3 Output data hold time CAS latency=2 tOH - - 3 3 ns 2 CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 CAS latency=3 5.4 6 6 6 ns 2 CLK to output in Hi-Z CAS latency=2 tSHZ - - 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.

REV.1.0 (August.2002) SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n S A S A S E D Q M BA 0,1 A10/ AP A11 A9~A0 NOTE Register Mode register set H X L L L L X OP code 1,2 Auto refresh H 3 Entry H L L L L H X X L H H H 3 Refresh Self refres h Exit L H H X X X X X Bank active & row addr. H X L L H H X V Row address Auto precharge disable L 4 Read & column address Auto precharge disable H X L H L H X V H Column Address (A0 ~ A9) 4,5 Auto precharge disable L Column Address (A0 ~ A9)

4 Write &

H 4,5 Burst Stop H X L L H L X X 6 Bank selection V L Precharg e All banks H X L L H L X X H X H X X X Entry H L L V V V X Clock suspend or active power down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge power down mode Exit L H L V V V X X DQM H X V X 7 H X X X No operation command H X L H H H X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV.1.0 (August.2002) TIMING DIAGRAMS Please refer to attached timing diagram chart (II) PACKAGING INFORMATION Unit : mm HSD8M32F4V Connector Configuration - Module PCB Bottom: AMP 177986-2, 0.8mm Free Height Plugs, 60pins - Board top, Module PCB Top:AMP 5-179180-2,0.8mm Free Height Receptacles , 60pins HSD8M32F4VA 0.90 0.90 82.68. 5.00 0.90 30.00 0.90 5.00 Bottom View 9.00 7.75 4.60 MAIN BOARD 1.30

REV.1.0 (August.2002) Connector Configuration - Module PCB Bottom: AMP 177984-2, 0.8mm Free Height Plugs, 60pins - Board top, Module PCB Top : AMP 177983-2,0.8mm Free Height Receptacles , 60pins

ORDERING INFORMATION

5.00 3.75 4.60 MAIN BOARD 1.30 0.90 0.90 82.68. 5.00 0.90 30.00 0.90 5.00 Bottom View

REV.1.0 (August.2002) Part Number Density Org. Package Ref. Vcc Feature MAX.frq HSD8M32F4V-13 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 133MHz HSD8M32F4V-12 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 125MHz HSD8M32F4V-10 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=2 100MHz HSD8M32F4V-10L 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 100MHz HSD8M32F4VA-13 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 133MHz HSD8M32F4VA-12 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 125MHz HSD8M32F4VA-10 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=2 100MHz HSD8M32F4VA-10L 32MByte 8Mx 32 120 Pin SMM 4K 3.3V CL=3 100MHz