HSD8M32B4 HANBIT | Alldatasheet

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Technical content

URL:www.hbe.co.kr - 1 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). GENERAL DESCRIPTION The HSD8M32B4 is a 8M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of four CMOS 1M x 16 bit x 4banks Synchronous DRAMs in TSOP -II packages mounted on a 144-pin, FR-4-printed circuit board. Two 0.01uF decoupling capacitor is mounted on the printed circuit board in parallel for each SDRAM. The HSD8M32B4 is a SO-DIMM designed. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cy cle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

  • Part Identification HSD8M32B4-10 : 100MHz ( CL=2) HSD8M32B4-10L : 100MHz ( CL=3) HSD8M32B4-12 : 125MHz ( CL=3) HSD8M32B4-13 :133MHz ( CL=3)
  • Burst mode operation
  • Auto & self refresh capability (4096 Cycles/64ms)
  • LVTTL compatible inputs and outputs
  • Single 3.3V ±0.3V power supply
  • MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
  • All inputs are sampled at the positive going edge of the system clock
  • FR4-PCB design
  • The used device is K4S641632D-TC Synchronous DRAM Module 32Mbyte ( 8M x 32-Bit ) 144pin SO-DIMM based on 4Mx16, 4Banks, 4K Ref., 3.3V Part No . HSD8M32B4

URL:www.hbe.co.kr - 2 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). PIN ASSIGNMENT *Pin Names Pin Name Function Pin Name Function A0 ~ A11 Address input (Multiplexed) BA0 ~ BA1 Select bank DQ0 ~ DQ31 Data input/output CLK0,CLK1 Clock input CKE0 Clock enable input /CS0, /CS1 Chip select input /RAS Row address strobe CAS Column address strobe /WE Write enable DQM0 ~ 3 DQM Vcc Power supply (3.3V) Vss Ground SDA Serial data I/O SCL Serial clock DU Do ¢ t use□ NC No connection PIN Front PIN Back PIN Frontl PIN Back PIN Front PIN Back

1 Vss 2 Vss 49 DQ13 50 NC 97 DQ22 98 NC

3 DQ0 4 NC 51 DQ14 52 NC 99 DQ23 100 NC

5 DQ1 6 NC 53 DQ15 54 NC 101 VCC 102 VCC

7 DQ2 8 NC 55 Vss 56 Vss 103 A6 104 A7

9 DQ3 10 NC 57 NC 58 NC 105 A8 106 BA0

11 VCC 12 VCC 59 NC 60 NC 107 Vss 108 Vss

13 DQ4 14 NC 61 CLK0 62 CKE0 109 A9 110 BA1

15 DQ4 16 NC 63 VCC 64 VCC 111 A10 112 A11

17 DQ6 18 NC 65 /RAS 66 /CAS 113 VCC 114 VCC

19 DQ7 20 NC 67 /WE 68 NC 115 DQM2 116 NC

21 Vss 22 Vss 69 /CS0 70 NC 117 DQM3 118 NC

23 DQM0 24 NC 71 /CS1 72 NC 119 Vss 120 Vss

25 DQM1 26 NC 73 DU 74 CLK1 121 DQ24 122 NC

27 VCC 28 VCC 75 Vss 76 Vss 123 DQ25 124 NC

29 A0 30 A3 77 NC 78 NC 125 DQ26 126 NC

31 A1 32 A4 79 NC 80 NC 127 DQ27 128 NC

33 A2 34 A5 81 VCC 82 VCC 129 VCC 130 VCC

35 Vss 36 Vss 83 DQ16 84 NC 131 DQ28 132 NC

37 DQ8 38 NC 85 DQ17 86 NC 133 DQ29 134 NC

39 DQ9 40 NC 87 DQ18 88 NC 135 DQ30 136 NC

41 DQ10 42 NC 89 DQ19 90 NC 137 DQ31 138 NC

43 DQ11 44 NC 91 Vss 92 Vss 139 Vss 140 Vss

45 VCC 46 VCC 93 DQ20 94 NC 141 SDA 142 SCL

47 DQ12 48 NC 95 DQ21 96 NC 143 VCC 144 VCC

URL:www.hbe.co.kr - 3 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). CKE CLK CAS DQ0-15 RAS L DQM CE UDQM WE A0 -A11 BA0 -1 /CAS /RAS CKE0 CKE CLK CAS DQ16-31 RAS L DQM CE UDQM WE A0 -A11 BA0 -1 CKE CLK CAS DQ8-15 RAS L DQM CE UDQM WE A0 -A11 BA0 -1 CKE CLK CAS DQ16-31 RAS L DQM CE UDQM WE A0 -A11 BA0 -1 FUNCTIONAL BLOCK DIAGRAM DQ0-31 Vcc Vss /CE0 /WE A0 - A11 BA0-1 DQM0 CLK DQM2 DQM1 DQM3 DQM0 DQM1 DQM2 DQM3 /CE1 Two 0.01uF Capacitor per each SDRAM

URL:www.hbe.co.kr - 4 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA8 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 3 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Voltage on Any Pin Relative to Vss VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 4W Storage Temperature TSTG -55oC to 150oC Short Circuit Output Current IOS 50mA Notes : Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

URL:www.hbe.co.kr - 5 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNIT NOTE Address(A0~A11, BA0~BA1) CADD 10 20 pF 2 /RAS, /CAS, /WE C IN 10 20 pF 2 CKE(CKE0) CCKE 10 20 pF 2 Clock (CLK0) CCLK 10 16 pF 1 /CE (/CE1) CCS 10 20 pF 2 DQM (DQM0 ~ DQM3) CDQM 10 20 pF 2 DQ (DQ0 ~ DQ31) COUT 16 26 pF 3 Notes : 1. –13 only specify a maximum value of 3.5pF 2. –13 only specify a maximum value of 3.8pF 3. – 13 only specify a maximum value of 6.0pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) VERSION PARAMETER SYMBOL TEST CONDITION -13 -12 -10 -10L UNIT NOTE Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0mA 440 440 400 400 mA 1 ICC2P CKE ≤ VIL(max) tCC=10ns 4 mA Precharge standby current in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ 4 mA

URL:www.hbe.co.kr - 6 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). ICC2N CKE ≥ VIH(min) CS* ≥ VIH(min), tCC=10ns Input signals are changed one time during 20ns Precharge standby current in non power-down mode ICC2NS CKE ≥ VIH(min) CLK ≤ VIL(max), tCC=∞ Input signals are stable mA ICC3P CKE ≤ VIL(max), tCC=10ns 12 Active standby current in power-down mode ICC3PS CKE&CLK ≤ VIL(max) tCC=∞ mA ICC3N CKE≥VIH(min), CS*≥VIH(min), tCC=10ns Input signals are changed one time during 20ns 100 Active standby current in non power-down mode (One bank active) ICC3NS CKE≥VIH(min) CLK ≤VIL(max), tCC=∞ Input signals are stable mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 540 520 500 500 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 540 520 500 500 mA 2 4 mA G Self refresh current ICC6 CKE ≤ 0.2V 1.6 mA F Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT AC Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2

URL:www.hbe.co.kr - 7 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) 100 ns Row cycle time tRC(min) 65 68 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + 20 ns Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. +3.3V Vtt=1.4V 50Ω 50pF DOUT Z0=50Ω 1200Ω 870Ω 50pF* DOUT VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

URL:www.hbe.co.kr - 8 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -A -8 -H -L PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT NOTE CAS latency=3 7.5 8 10 10 CLK cycle time CAS latency=2 tCC 1000 1000 1000 1000 ns 1 CAS latency=3 5.4 6 6 6 CLK to valid output delay CAS latency=2 tSAC - - 6 7 ns 1,2 CAS latency=3 2.7 3 3 3 Output data hold time CAS latency=2 tOH - - 3 3 ns 2 CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 CAS latency=3 5.4 6 6 6 ns 2 CLK to output in Hi-Z CAS latency=2 tSHZ - - 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter.

URL:www.hbe.co.kr - 9 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n S A S A S E D Q M BA 0,1 A10/ AP A11 A9~A0 NOTE Register Mode register set H X L L L L X OP code 1,2 Auto refresh H 3 Entry H L L L L H X X L H H H 3 Refresh Self refresh Exit L H H X X X X X Bank active & row addr. H X L L H H X V Row address Auto precharge disable L 4 Read & column address Auto precharge disable H X L H L H X V H Column Address (A0 ~ A9) 4,5 Auto precharge disable L Column Address (A0 ~ A9)

4 Write &

H 4,5 Burst Stop H X L L H L X X 6 Bank selection V L Precharge All banks H X L L H L X X H X H X X X Entry H L L V V V X Clock suspend or active power down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge power down mode Exit L H L V V V X X DQM H X V X 7 H X X X No operation command H X L H H H X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

URL:www.hbe.co.kr - 10 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002). TIMING DIAGRAMS Please refer to timing diagram chart (II) PACKAGING INFORMATION

0.25 MAX

2.54 MIN

1.27 (Solder & Gold Plating) Gold: 1.04±0.10 Solder: 0.914±0.10 1.27±0.08mm 10.16 107.95 ± 20 2.03 1.27 1.00 95.25 6.35 3.2 44.45 3.38 10.16 17.8 ± 0.2 6.35 6.35

URL:www.hbe.co.kr - 11 - HANBit Electronics Co.,Ltd REV.1.0 (August.2002).

ORDERING INFORMATION

Part Number Density Org. Package Ref. Vcc CL MAX.frq HSD8M32B4-10 32MByte 8Mx 32

144 Pin

4K 3.3V CL=2 100MHz HSD8M32B4-10L 32MByte 8Mx 32 4K 3.3V CL=3 100MHz HSD8M32B4-12 32MByte 8Mx 32 4K 3.3V CL=3 125MHz HSD8M32B4-13 32MByte 8Mx 32 4K 3.3V CL=3 133MHz