HSD32M72D18A-12

HSD32M72D18A HANBIT | Alldatasheet

Document overview

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Technical content

REV.1.0 (August.2002) - 1 - GENERAL DESCRIPTION The HSD32M72D18A is a 32M x 72 bit Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 16M x 8 bit with 4banks Synchronous DRAMs in TSOP -II 400mil packages and 2K EEPROM in 8 -pin TSSOP package on a 168-pin glass-epoxy. Two 0.33uF-decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD32M72D18A is a DIMM (Dual in line Memory Module) and is intended for mounting into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high perf ormance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• Part Identification HSD32M72D18A-F/10L : 100MHz (CL=3) HSD32M72D18A-F/10 : 100MHz (CL=2) HSD32M72D18A-F/12 : 125MHz (CL=3) HSD32M72D18A-F/13 : 133MHz (CL=3) F means Auto & Self refresh with Low-Power (3.3V)
• Burst mode operation
• Auto & self refresh capability (4096 Cycles/64ms)
• LVTTL compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• MRS cycle with address key programs - Latency (Access from column address) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 8M x 8bit , 4Banks SDRAM Synchronous DRAM Module 256Mbyte (32Mx72bit), DIMM with ECC based on 16Mx8, 4Banks, 4K Ref., 3.3V Part No . HSD32M72D18A (Unbuffered)

REV.1.0 (August.2002) - 2 - PIN ASSIGNMENT PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol

1 Vss 29 DQM1 57 DQ18 85 Vss 113 DQM5 141 DQ50

2 DQ0 30 /CE0 58 DQ19 86 DQ32 114 /CE1 142 DQ51

3 DQ1 31 NC 59 Vcc 87 DQ33 115 /RAS 143 Vcc

4 DQ2 32 Vss 60 DQ20 88 DQ34 116 Vss 144 DQ52

5 DQ3 33 A0 61 NC 89 DQ35 117 A1 145 NC

6 Vcc 34 A2 62 NC 90 Vcc 118 A3 146 NC

7 DQ4 35 A4 63 CKE1 91 DQ36 119 A5 147 NC

8 DQ5 36 A6 64 Vss 92 DQ37 120 A7 148 Vss

9 DQ6 37 A8 65 DQ21 93 DQ38 121 A9 149 DQ53

10 DQ7 38 A10 66 DQ22 94 DQ39 122 BA0 150 DQ54

11 DQ8 39 BA1 67 DQ23 95 DQ40 123 A11 151 DQ55

12 Vss 40 Vcc 68 Vss 96 Vss 124 Vcc 152 Vss

13 DQ9 41 Vcc 69 DQ24 97 DQ41 125 CLK1 153 DQ56

14 DQ10 42 CLK0 70 DQ25 98 DQ42 126 NC 154 DQ57

15 DQ11 43 Vss 71 DQ26 99 DQ43 127 Vss 155 DQ58

16 DQ12 44 NC 72 DQ27 100 DQ44 128 CKE0 156 DQ59

17 DQ13 45 /CE2 73 Vcc 101 DQ45 129 /CE3 157 Vcc

18 Vcc 46 DQM2 74 DQ28 102 Vcc 130 DQM6 158 DQ60

19 DQ14 47 DQM3 75 DQ29 103 DQ46 131 DQM7 159 DQ61

20 DQ15 48 NC 76 DQ30 104 DQ47 132 NC 160 DQ62

21 CB0 49 Vcc 77 DQ31 105 CB4 133 Vcc 161 DQ63

22 CB1 50 NC 78 Vss 106 CB5 134 NC 162 Vss

23 Vss 51 NC 79 CLK2 107 Vss 135 NC 163 CLK3

24 NC 52 CB2 80 NC 108 NC 136 CB6 164 NC

25 NC 53 CB3 81 WP 109 NC 137 CB7 165 SA0

26 Vcc 54 Vss 82 SDA 110 Vcc 138 Vss 166 SA1

27 /WE 55 DQ16 83 SCL 111 /CAS 139 DQ48 167 SA2

28 DQM0 56 DQ17 84 Vcc 112 DQM4 140 DQ49 168 Vcc

• These pins are not used in this module ** These pins should be NC in the sy stem which does not support SPD *Pin Names VREF : Power supply for reference CB0~7 : Check bit (Data in/data -out) CLK0 ~ CLK3 : Clock input CKE0 ~ CKE1 : Colck enable input /CE0 ~ /CE3 : Chip enable input Vcc : Power supply Vss : Gr ound SDA : Serial data I/O SCL : Serial clock SA0 ~ 2 : Address in EEPROM

REV.1.0 (August.2002) - 3 - FUNCTIONAL BLOCK DIAGRAM

REV.1.0 (August.2002) - 4 - PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System clock Active on the positive going edge to sample all inputs. /CE Chip enable Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A11 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11, Column address : CA0 ~ CA9 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. DQM0 ~ 7 Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input/output Data inputs/outputs are multiplexed on the same pins. Vcc/Vss Power supply/ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Voltage on Any Pin Relative to Vss VIN ,OUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 18W Storage Temperature TSTG -55oC to 150oC Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

REV.1.0 (August.2002) - 5 - DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) DESCRIPTION SYMBOL MIN MAX UNITS Clock CCLK 18 25 pF /RAS, /CAS,/WE,/CE, CKE, DQM CIN 50 95 pF Address CADD 50 95 pF DQ (DQ0 ~ DQ7) COUT 13 18 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) VERSION PARAMETER SYMBOL TEST CONDITION -13 -12 -10 10L UNIT NOT E Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0mA 2160 2160 1980 1980 mA 1 ICC2P CKE ≤ VIL(max) tCC=10ns 18 mA Precharge standby current in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ 18 mA ICC2N CKE ≥ VIH(min) CS* ≥ VIH(min), tCC=10ns Input signals are changed one time during 20ns

360 Precharge standby current

non power-down mode ICC2NS CKE ≥ VIH(min) CLK ≤ VIL(max), tCC=∞ Input signals are stable 126 mA ICC3P CKE ≤ VIL(max), tCC=10ns 90 Active standby current in power-down mode ICC3PS CKE&CLK ≤ VIL(max) tCC=∞ 90 mA

REV.1.0 (August.2002) - 6 - ICC3N CKE≥VIH(min), CS*≥VIH(min), tCC=10ns Input signals are changed one time during 20ns

540 Active standby current in

(One bank active) ICC3NS CKE≥VIH(min) CLK ≤VIL(max), tCC=∞ Input signals are stable 360 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 2700 2610 2250 2250 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 3960 3960 3780 3780 mA 2 27 mA Self refresh current ICC6 CKE ≤ 0.2V 14.4 mA Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT AC Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 +3.3V 1200Ω 870Ω 50pF* DOUT Vtt=1.4V 50Ω 50pF DOUT Z0=50Ω VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit

REV.1.0 (August.2002) - 7 - OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) 100 ns Row cycle time tRC(min) 65 68 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2 Last data in to Active delay tDAL(min) 2 CLK + 20 ns - Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. .5. For -8/H/L/10, tRDL=1CLK and tDAL=1CLK+20ns is also supported . ( recommend : tRDL=2CLK and tDAL=2CLK + 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 -12 -10 -10L PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT NOTE CAS latency=3 7.5 8 10 10 CLK cycle time CAS latency=2 tCC 1000 1000 1000 1000 ns 1 CAS latency=3 5.4 6 6 6 CLK to valid output delay CAS latency=2 tSAC - - 6 7 ns 1,2 CAS latency=3 2.7 3 3 3 Output data hold time CAS latency=2 tOH - - 3 3 ns 2 CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3

REV.1.0 (August.2002) - 8 - Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 CAS latency=3 5.4 6 6 6 ns 2 CLK to output in Hi-Z CAS latency=2 tSHZ - - 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n E A S A S E D Q M BA 0,1 A10/ AP A11 A9~A0 NOTE Register Mode register set H X L L L L X OP code 1,2 Auto refresh H 3 Entry H L L L L H X X L H H H 3 Refresh Self refres h Exit L H H X X X X X Bank active & row addr. H X L L H H X V Row address Auto pre charge disable L 4 Read & column address Auto precharge disable H X L H L H X V H Column Address (A0 ~ A9) 4,5 Auto precharge disable L Column Address (A0 ~ A9)

4 Write &

H 4,5 Burst Stop H X L L H L X X 6 Bank selection V L Precharge All banks H X L L H L X X H X H X X X Entry H L L V V V X Clock suspend or active power down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge power down mode Exit L H L V V V X X DQM H X V X 7 H X X X No operation command H X L H H H X X (V=Valid, X=Don't care, H=Logic high, L=Logic low)

REV.1.0 (August.2002) - 9 - Notes : 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) PACKAGING INFORMATION Unit : inch [mm] PCB Size : 1.27 ±0.008 [ ±0.20 ]

REV.1.0 (August.2002) - 10 -

ORDERING INFORMATION

Part Number Density Org. Package Ref. Vcc MODE MAX.frq HSD32M72D18A-13 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 133MHz HSD32M72D18A-12 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 125MHz HSD32M72D18A-10L 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 100MHz HSD32M72D18A-10 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL2 100MHz HSD32M72D18A-F13 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 133MHz HSD32M72D18A-F12 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 125MHz HSD32M72D18A-F10L 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL3 100MHz HSD32M72D18A-F10 256MByte 32M x 72 168 Pin-DIMM 4K 3.3V ECC/ Unbuffered CL2 100MHz F means Auto & Self refresh with Low-Power (3.3V)