HSD128M72B9K

HSD128M72B9K HANBIT | Alldatasheet

Document overview

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Technical content

REV.0.0(January. 2003) 1 GENERAL DESCRIPTION The HSD128M72B9K is a 128M x 72 bit Synchronous Dynamic RAM high density memory module. The module consists of nine CMOS 128M x 8 bit with 4banks Synchronous DRAMs in TSOP -II 400mil packages on a 144 -pin glass- epoxy substrate. One or two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD128M72B9K is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• JEDEC standard 3.3V power supply
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible with multiplexed address
• Separate power and ground planes to improve immunity
• Height : 1.250 inches
• MRS cycle with address key programs - CAS latency (2 & 3) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 16M x 8bit x 4Banks Synchronous DRAM
• Part Identification HSD128M72B9K-F/10L : 100MHz (CL=3) HSD128M72B9K-F/10 : 100MHz (CL=2) HSD128M72B9K-F/12 : 125MHz (CL=3) HSD128M72B9K-F/13 : 133MHz (CL=3) ** F means Auto & Self refresh with Low-Power (3.3V) Synchronous DRAM Module 1024Mbyte (128Mx72Bit), 8K Ref., 3.3V ECC Unbuffered SO-DIMM, Part No. HSD128M72B9K

REV.0.0(January. 2003) 2 PIN ASSIGNMENT No. Front No. Back No. Front No. Back

1 Vss 2 Vss 71 /CS1 72 NC

3 DQ0 4 DQ32 73 NC 74 CLK1

5 DQ1 6 DQ33 75 Vss 76 Vss

7 DQ2 8 DQ34 77 CB2 78 CB6

9 DQ3 10 DQ35 79 CB3 80 CB7

11 VCC 12 VCC 81 VCC 82 VCC

13 DQ4 14 DQ36 83 DQ16 84 DQ48

15 DQ5 16 DQ37 85 DQ17 86 DQ49

\`17 DQ6 18 DQ38 87 DQ18 88 DQ50

19 DQ7 20 DQ39 89 DQ19 90 DQ51

21 Vss 22 Vss 91 Vss 92 Vss

23 DQM0 24 DQM4 93 DQ20 94 DQ52

25 DQM1 26 DQM5 95 DQ21 96 DQ53

27 VCC 28 VCC 97 DQ22 98 DQ54

29 A0 30 A3 99 DQ23 100 DQ55

31 A1 32 A4 101 VCC 102 VCC

33 A2 34 A5 103 A6 104 A7

35 Vss 36 Vss 105 A8 106 BA0

37 DQ8 38 DQ40 107 Vss 108 Vss

39 DQ9 40 DQ41 109 A9 110 BA1

41 DQ10 42 DQ42 111 A10_AP 112 A11

43 DQ11 44 DQ43 113 VCC 114 VCC

45 VCC 46 VCC 115 DQM2 116 DQM6

47 DQ12 48 DQ44 117 DQM3 118 DQM7

49 DQ13 50 DQ45 119 Vss 120 Vss

51 DQ14 52 DQ46 121 DQ24 122 DQ56

53 DQ15 54 DQ47 123 DQ25 124 DQ57

55 Vss 56 Vss 125 DQ26 126 DQ58

57 CB0 58 CB4 127 DQ27 128 DQ59

59 CB1 60 CB5 129 VCC 130 VCC

131 DQ28 132 DQ60

133 DQ29 134 DQ61

61 CLK0 62 CKE0 135 DQ30 136 DQ62

63 VCC 64 VCC 137 DQ31 138 DQ63

65 /RAS 66 /CAS 139 Vss 140 Vss 67 /WE 68 CKE1 141 SDA 142 SCL 69 /CS0 70 A12 143 VCC 144 VCC ** These pins should be NC in the system which does not support SPD

REV.0.0(January. 2003) 3 Functional Block Diagram U5U /CS U6U /CS U7U /CS U8U /CS U9U /CS U4U /CS U3U /CS U2U /CS U1U /CS DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U9L BA(0:1) CLK CB(0:7) /CS Add(0:12) /RAS /CAS /WE CKE(0:1) BA(0:1) CLK0 /CS0 DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U2L BA(0:1) /CS CLK DQ(8:15) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U4L BA(0:1) CLK DQ(24:31) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U3L BA(0:1) CLK DQ(16:23) /CS /CS DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U5L BA(0:1) /CS CLK DQ(32:39) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U6L BA(0:1) /CS CLK DQ(40:47) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U8L BA(0:1) CLK DQ(56:63) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE(0:1) U7L BA(0:1) CLK DQ(48:55) /CS /CS /CS1 A0 A1 A2 SCL Serial PD SDA WP SA0 SA1 SA2 VCC VSS One or two 0.1uF Capacitors per each SDRAM To all SDRAMs CLK1 DQ(0:7)DQ(0:7) DQM0 DQMDQM1 DQMDQM2 DQMDQM3 DQMDQM1 DQMDQM4 DQMDQM5 DQMDQM6 DQMDQM7 47K Add(0:12) /RAS /CAS /WE CKE(0:1) U1L BA(0:1) /CS CLK DQM

REV.0.0(January. 2003) 4 PIN FUNCTION DESCRIPTION Pin Name Input Function CLK0~CLK1 System clock Active on the positive going edge to sample all inputs. /CS0~/CS1 Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE0, CKE1 Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from /CAS, /WE active. DQM0 ~ 7 Data input / output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 63 Data input / output Data inputs/outputs are multiplexed on the same pins. CB0~7 Check bit Check bits for ECC VCC / VSS Power supply / ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Voltage on Any Pin Relative to Vss VIN , VOUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 18W Storage Temperature TSTG -55oC to 150oC Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

REV.0.0(January. 2003) 5 DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns. 3. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) PARAMETER SYMBOL MIN MAX UNITS Input Capacitance (A0~A12, BA0~BA1) CIN1 45 90 pF Input Capacitance (/RAS, /CAS, /WE) CIN2 45 90 pF Input Capacitance (CKE0 ~ CKE1) CIN3 35 60 pF Input Capacitance (CLK0 ~ CLK1) CIN4 25 45 pF Input Capacitance (/CS0 ~ /CS1) CIN5 35 60 pF Input Capacitance (DQM0 ~ DQM1) CIN6 10 25 pF Data Input Capacitance (DQ0 ~ DQ63) CIN7 15 30 pF Data Input Capacitance (CB0 ~ CB7) COUT 15 30 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) VERSION PARAMETER SYMBOL TEST CONDITION -13 -12 -10 -10L UNIT NOTE Operating current (One bank active) ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0mA 1080 990 990 990 mA 1 ICC2P CKE ≤ VIL(max) tCC=10ns 36 mA Precharge standby current in power-down mode ICC2PS CKE & CLK ≤ VIL(max) tCC=∞ 36 mA Precharge standby current in non power-down mode ICC2N CKE ≥ VIH(min) CS* ≥ VIH(min), tCC=10ns Input signals are changed one time during 20ns 360 mA

REV.0.0(January. 2003) 6 ICC2NS CKE ≥ VIH(min) CLK ≤ VIL(max), tCC=∞ Input signals are stable 180 ICC3P CKE ≤ VIL(max), tCC=10ns 72 Active standby current in power-down mode ICC3PS CKE&CLK ≤ VIL(max) tCC=∞ mA ICC3N CKE≥VIH(min), CS*≥VIH(min), tCC=10ns Input signals are changed one time during 20ns 450 Active standby current in non power-down mode (One bank active) ICC3NS CKE≥VIH(min) CLK ≤VIL(max), tCC=∞ Input signals are stable 315 mA Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 1260 1260 1170 1170 mA 1 Refresh current ICC5 tRC ≥ tRC(min) 2160 1980 1890 1890 mA 2 54 mA 3 Self refresh current ICC6 CKE ≤ 0.2V 27 mA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (Vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT AC Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 +3.3V Vtt=1.4V 50Ω 50pF DOUT Z0=50Ω 1200Ω 870Ω 50pF* DOUT VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load (Fig. 2) AC output load circuit

REV.0.0(January. 2003) 7 OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) VERSION PARAMETER SYMBOL -13 -12 -10 -10L UNIT NOTE Row active to row active delay tRRD(min) 15 16 20 20 ns 1 RAS to CAS delay tRP(min) 20 20 20 20 ns 1 Row precharge time tRP(min) 20 20 20 20 ns 1 tRAS(min) 45 48 50 50 ns 1 Row active time tRAS(max) 100 ns Row cycle time tRC(min) 65 68 70 70 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 CAS latency=3 2 Number of valid output data CAS latency=2 - 1 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . (Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) -13 -12 -10 -10L PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNIT NOTE CAS latency=3 7.5 8 10 10 CLK cycle time CAS latency=2 tCC 1000 1000 1000 1000 ns 1 CAS latency=3 5.4 6 6 6 CLK to valid output delay CAS latency=2 tSAC - - 6 7 ns 1,2 Output data hold time CAS latency=3 tOH 2.7 3 3 3 ns 2

REV.0.0(January. 2003) 8 CAS latency=2 - - 3 3 CLK high pulse width tCH 2.5 3 3 3 ns 3 CLK low pulse width tCL 2.5 3 3 3 ns 3 Input setup time tSS 1.5 2 2 2 ns 3 Input hold time tSH 0.8 1 1 1 ns 3 CLK to output in Low-Z tSLZ 1 1 1 1 ns 3 CAS latency=3 5.4 6 6 6 ns 2 CLK to output in Hi-Z CAS latency=2 tSHZ - - 6 7 ns Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n /CS /RAS /CAS /WE DQM BA0,1 A10/AP A11,A12, A9~A0 NOTE Register Mode register set H X L L L L X OP code 1,2 Auto refresh H 3 Entry H L L L L H X X L H H H 3 Refresh Self refresh Exit L H H X X X X X Bank active & row addr. H X L L H H X V Row address Auto precharge disable L 4 Read & column address Auto precharge disable H X L H L H X V H Column Address (A0 ~ A9) 4,5 Auto precharge disable L Column Address (A0 ~ A9) Write & column address Auto precharge disable H X L H L L X V H 4,5 Burst Stop H X L L H L X X 6 Bank selection V L Precharge All banks H X L L H L X X H X H X X X Entry H L L V V V X Clock suspend or active power down Exit L H X X X X X X H X X X Entry H L L H H H X H X X X Precharge power down mode Exit L H L V V V X X DQM H X V X 7

REV.0.0(January. 2003) 9 H X X X No operation command H X L H H H X X (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

REV.0.0(January. 2003) 10 PACKAGING INFORMATION Unit : mm PCB Thickness: 1.0± 0.1mm Tolerances : ± 0.15 unless otherwise specified Immersion Gold PCB Pattern

REV.0.0(January. 2003) 11

ORDERING INFORMATION

Part Number Density Org. Package Ref. Vcc Bank MAX.frq HSD128M72B9K-13 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 133MHz HSD128M72B9K-12 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 125MHz HSD128M72B9K-10L 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 100MHz HSD128M72B9K-10 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL2 100MHz HSD128M72B9K-F13 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 133MHz HSD128M72B9K-F12 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 125MHz HSD128M72B9K-F10L 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL3 100MHz HSD128M72B9K-F10 1024MByte 128M x 72 144 Pin-SODIMM 8K 3.3V 4Bank CL2 100MHz F means Auto & Self refresh with Low-Power (3.3V)