HSD128M32B8A

HSD128M32B8A DLGHANBIT | Alldatasheet

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DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) GENERAL DESCRIPTION The HSD128M32B8A is a 128M x 32 bit Synchronous Dynamic RAM high density memory module. The module consists of nine CMOS 128M x 32 bit with 4banks Synchronous DRAMs in TSOP -II 400mil packages on a 144 -pin glass-epoxy substrate. One or two 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each SDRAM. The HSD128M32B8A is a SO-DIMM(Small Outline Dual in line Memory Module) and is intended for mounting into 144-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performanc e memory system applications All module components may be powered from a single 3.3V DC power supply and all inputs and outputs are LVTTL-compatible.

FEATURES

• JEDEC standard 3.3V power supply
• Burst mode operation
• Auto & self refresh capability (8192 Cycles/64ms)
• LVTTL compatible with multiplexed address
• Separate power and ground planes to improve immunity
• Height : 1.250 inches
• MRS cycle with address key programs - CAS latency (3) - Burst length (1, 2, 4, 8 & Full page) - Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock
• The used device is 16M x 8bit x 4Banks Synchronous DRAM
• Part Identification HSD128M32B8A-13 : 133MHz (CL=3) Synchronous DRAM Module 512Mbyte (128Mx32Bit), 8K Ref., 3.3V Part No. HSD128M32B8A All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) PIN ASSIGNMENT No. Front No. Back No. Front No. Back

1 Vss 2 Vss 71 /CS1 72 NC

3 DQ0 4 NC 73 NC 74 CLK1

5 DQ1 6 NC 75 Vss 76 Vss

7 DQ2 8 NC 77 NC 78 NC

9 DQ3 10 NC 79 NC 80 NC

11 VCC 12 VCC 81 VCC 82 VCC

13 DQ4 14 NC 83 DQ16 84 NC

15 DQ5 16 NC 85 DQ17 86 NC

17 DQ6 18 NC 87 DQ18 88 NC

19 DQ7 20 NC 89 DQ19 90 NC

21 Vss 22 Vss 91 Vss 92 Vss

23 DQM0 24 NC 93 DQ20 94 NC

25 DQM1 26 NC 95 DQ21 96 NC

27 VCC 28 VCC 97 DQ22 98 NC

29 A0 30 A3 99 DQ23 100 NC

31 A1 32 A4 101 VCC 102 VCC

33 A2 34 A5 103 A6 104 A7

35 Vss 36 Vss 105 A8 106 BA0

37 DQ8 38 NC 107 Vss 108 Vss

39 DQ9 40 NC 109 A9 110 BA1

41 DQ10 42 NC 111 A10_AP 112 A11

43 DQ11 44 NC 113 VCC 114 VCC

45 VCC 46 VCC 115 DQM2 116 NC

47 DQ12 48 NC 117 DQM3 118 NC

49 DQ13 50 NC 119 Vss 120 Vss

51 DQ14 52 NC 121 DQ24 122 NC

53 DQ15 54 NC 123 DQ25 124 NC

55 Vss 56 Vss 125 DQ26 126 NC

57 NC 58 NC 127 DQ27 128 NC

59 NC 60 NC 129 VCC 130 VCC

131 DQ28 132 NC

133 DQ29 134 NC

61 CLK0 62 CKE0 135 DQ30 136 NC

63 VCC 64 VCC 137 DQ31 138 NC

65 /RAS 66 /CAS 139 Vss 140 Vss 67 /WE 68 CKE1 141 SDA 142 SCL 69 /CS0 70 A12 143 VCC 144 VCC ** These pins should be NC in the system which does not support SPD All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) Functional Block Diagram Add(0:12) /RAS /CAS /WE CKE BA(0:1) /CS0 CLK Add(0:12) /RAS /CAS /WE CKE0 BA(0:1) CLK0 /CS0 DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) /CS0 CLK DQ(8:15) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) CLK DQ(24:31) DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) CLK DQ(16:23) /CS0 /CS0 DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) /CS1 CLK DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) /CS1 CLK DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) CLK DQ(0:7) Add(0:12) /RAS /CAS /WE CKE BA(0:1) CLK /CS1 /CS1 /CS1 A0 A1 A2 SCL Serial PD SDA WP SA0 SA1 SA2 CLK1 DQ(0:7)DQ(0:7) DQMDQM0 DQMDQM1 DQMDQM2 DQMDQM3 DQM DQM DQM DQM 47K VCC VSS One or two 0.1uF Capacitors per each SDRAM To all SDRAMs CKE1 All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK0~CLK1 System clock Active on the positive going edge to sample all inputs. /CS0~/CS1 Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM CKE0, CKE1 Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. A0 ~ A12 Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12, Column address : CA0 ~ CA9, CA11 BA0 ~ BA1 Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. /RAS Row address strobe Latches row addresses on the positive going edge of the CLK with /RAS low. Enables row access & precharge. /CAS Column address strobe Latches column addresses on the positive going edge of the CLK with /CAS low. Enables column access. /WE Write enable Enables write operation and row precharge. Latches data in starting from /CAS, WE active. DQM0 ~ 3 Data input / output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) DQ0 ~ 31 Data input / output Data inputs/outputs are multiplexed on the same pins. VCC / VSS Power supply / ground Power and ground for the input buffers and the core logic. ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING Voltage on Any Pin Relative to Vss VIN , VOUT -1V to 4.6V Voltage on Vcc Supply Relative to Vss Vcc -1V to 4.6V Power Dissipation PD 8W Storage Temperature TSTG -55oC to 150oC Short Circuit Output Current IOS 50mA Notes: Permanent device damage may occur if " Absolute Maximum Ratings" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C) ) PARAMETER SYMBOL MIN TYP. MAX UNIT NOTE Supply Voltage Vcc 3.0 3.3 3.6 V Input High Voltage VIH 2.0 3.0 Vcc+0.3 V 1 Input Low Voltage VIL -0.3 0 0.8 V 2 Output High Voltage VOH 2.4 - - V IOH = -2mA Output Low Voltage VOL - - 0.4 V IOL = 2mA Input leakage current I LI -10 - 10 uA 3 Notes : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is  3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is  3ns. 3. Any input 0V  VIN  VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs. CAPACITANCE (VCC = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV) PARAMETER SYMBOL MIN MAX UNITS Input Capacitance (A0~A12, BA0~BA1) CIN1 30 45 pF Input Capacitance (/RAS, /CAS, /WE) CIN2 30 45 pF Input Capacitance (CKE0 ~ CKE1) CIN3 30 45 pF Input Capacitance (CLK0 ~ CLK1) CIN4 22 30 pF Input Capacitance (/CS0 ~ /CS1) CIN5 15 25 pF Input Capacitance (DQM0 ~ DQM1) CIN6 6 8 pF Data Input Capacitance (DQ0 ~ DQ63) CIN7 6 8 pF DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70°C) PARAMETER SYMBOL TEST CONDITION VERSION UNIT NOTE -13 Operating current (One bank active) ICC1 Burst length = 1 tRC  tRC(min) IO = 0mA 960 mA 1 Precharge standby current in power-down mode ICC2P CKE  VIL(max) tCC=10ns 8 mA ICC2PS CKE & CLK  VIL(max) tCC= 8 mA Precharge standby current in non power-down mode ICC2N CKE  VIH(min) CS*  VIH(min), tCC=10ns Input signals are changed one time during 20ns 160 mA All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) ICC2NS CKE  VIH(min) CLK  VIL(max), tCC= Input signals are stable Active standby current in power-down mode ICC3P CKE  VIL(max), tCC=10ns 40 mA ICC3PS CKE&CLK  VIL(max) tCC= Active standby current in non power-down mode (One bank active) ICC3N CKEVIH(min), CS*VIH(min), tCC=10ns Input signals are changed one time during 20ns 240 mA ICC3NS CKEVIH(min) CLK VIL(max), tCC= Input signals are stable 160 Operating current (Burst mode) ICC4 IO = 0 mA Page burst 4Banks Activated tCCD = 2CLKs 1160 mA 1 Refresh current ICC5 tRC  tRC(min) 1760 mA 2 Self refresh current ICC6 CKE  0.2V 12 mA 3 12 mA 4 Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noticed, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ). AC OPERATING TEST CONDITIONS (Vcc = 3.3V ± 0.3V, TA = 0 to 70°C) PARAMETER Value UNIT AC Input levels (Vih/Vil) 2.4/0.4 V Input timing measurement reference level 1.4 V Input rise and fall time tr/tf = 1/1 ns Output timing measurement reference level 1.4 V Output load condition See Fig. 2 +3.3V Vtt=1.4V 50 50pF DOUT Z0=50 1200 870 50pF* DOUT VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA (Fig. 1) DC output load circuit (Fig. 2) AC output load circuit All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) PARAMETER SYMBOL VERSION UNIT NOTE -13 Row active to row active delay tRRD(min) 15 ns 1 RAS to CAS delay tRP(min) 20 ns 1 Row precharge time tRP(min) 20 ns 1 Row active time tRAS(min) 45 ns 1 tRAS(max) 100 ns Row cycle time tRC(min) 65 ns 1 Last data in to row precharge tRDL(min) 2 CLK 2.5 Last data in to Active delay tDAL(min) 2 CLK + tRP - 5 Last data in to new col. address delay tCDL(min) 1 CLK 2 Last data in to burst stop tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK 3 Number of valid output data CAS latency=3 2 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported . (Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.) AC CHARACTERISTICS (AC operating conditions unless otherwise noted) PARAMETER SYMBOL -13 UNIT NOTE MIN MAX CLK cycle time CAS latency=3 tCC 7.5 1000 ns 1 CLK to valid output delay CAS latency=3 tSAC 5.4 ns 1,2 Output data hold time CAS latency=3 tOH 2.7 ns 2 CLK high pulse width tCH 2.5 ns 3 CLK low pulse width tCL 2.5 ns 3 Input setup time tSS 1.5 ns 3 Input hold time tSH 0.8 ns 3 CLK to output in Low-Z tSLZ 1 ns 3 CLK to output in Hi-Z CAS latency=3 tSHZ 5.4 ns 2 Notes : All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to the parameter. SIMPLIFIED TRUTH TABLE COMMAND CKE n-1 CKE n /CS /RAS /CAS /WE DQM BA0,1 A10/AP A11,A12, A9~A0 NOTE Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X Self refresh Entry L 3 Exit L H L H H H X X H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column Address Auto precharge disable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column Address Auto precharge disable H 4,5 Burst Stop H X L L H L X X 6 Precharge Bank selection H X L L H L X V L X All banks X H Clock suspend or active power down Entry H L H X X X X X L V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H X V X 7 No operation command H X H X X X X X L H H H (V=Valid, X=Don't care, H=Logic high, L=Logic low) Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected. If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) PACKAGING INFORMATION Unit : mm PCB Thickness: 1.0±0.1mm Tolerances : ± 0.15 unless otherwise specified Immersion Gold PCB Pattern

ORDERING INFORMATION

Part Number Density Org. Package Ref. Vcc Bank MAX.frq HSD128M32B8A-13 512MByte 128M x 32 144 Pin-SODIMM 8K 3.3V 4Bank CL3 133MHz 7F(#712), 274, Samsung-ro, Suwon-si, Gyeonggi-do, South Korea EMAIL : dlghbinfo@dlghb.co.kr http://www.dlghb.co.kr All d ata sheet.com

DLGHANBIT DLGHANBIT Confidential HSD128M32B8A URL : www.dlghb.co.kr DLG HANBIT Co.,Ltd REV 1.0(May. 2006) All d ata sheet.com