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AD7470 AD | Alldatasheet

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REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD7470/AD7472 Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

1.75 MSPS, 4 mW

10-Bit/12-Bit Parallel ADCs FUNCTIONAL BLOCK DIAGRAM T/H 10-/12-BIT SUCCESSIVE APPROXIMATION ADC OUTPUT DRIVERS AD7470/AD7472 VIN CONVST AGND DGND AVDD DVDD REF IN VDRIVE DB9 (DB11) DB0 CLK IN CS RD BUSY CONTROL LOGIC AD7470 IS A 10-BIT PART WITH DB0 TO DB9 AS OUTPUTS. AD7472 IS A 12-BIT PART WITH DB0 TO DB11 AS OUTPUTS.

FEATURES

Specified for V DD of 2.7 V to 5.25 V

1.75 MSPS for AD7470 (10-Bit)

1.5 MSPS for AD7472 (12-Bit)

AD7470: 3.34 mW Typ at 1.5 MSPS with 3 V Supplies 7.97 mW Typ at 1.75 MSPS with 5 V Supplies AD7472: 3.54 mW Typ at 1.2 MSPS with 3 V Supplies 8.7 mW Typ at 1.5 MSPS with 5 V Supplies Wide Input Bandwidth 70 dB Typ SNR at 500 kHz Input Frequency Flexible Power/Throughput Rate Management No Pipeline Delays High Speed Parallel Interface Sleep Mode: 50 nA Typ 24-Lead SOIC and TSSOP Packages GENERAL DESCRIPTION The AD7470/AD7472 are 10-bit/12-bit high speed, low power, successive-approximation ADCs. The parts operate from a single 2.7 V to 5.25 V power supply and feature throughput r ates up to 1.5 MSPS for the 12-bit AD7472 and up to 1.75 MSPS for the 10-bit AD7470. The parts contain a low noise, wide band- width track/hold amplifier that can handle input frequencies in excess of 1 MHz. The conversion process and data acquisition are controlled using standard control inputs allowing easy interfacing to microprocessors or DSPs. The input signal is sampled on the falling edge of CONVST and conversion is also initiated at this point. The BUSY goes high at the start of conversion and goes low 531.66 ns after falling edge of CONVST (AD7472 with a clock frequency of 26 MHz) to indicate that the conversion is complete. There are no pipelined delays associated with the part. The conversion result is accessed via standard CS and RD sig- nals over a high speed parallel interface. The AD7470/AD7472 uses advanced design techniques to achieve very low power dissipation at high throughput rates. With 3 V supplies and 1.5 MSPS throughput rate, the AD7470 typi- cally consumes, on average, just 1.1 mA. With 5 V supplies and

1.75 MSPS, the average current consumption is typically

1.6 mA. The part also offers flexible power/throughput rate management. Operating the AD7470 with 3 V supplies and 500 kSPS throughput reduces the current consumption to 713 µA. At 5 V supplies and 500 kSPS, the part consumes 944 µA. It is also possible to operate the parts in an auto sleep mode, where the part wakes up to do a conversion and automatically enters sleep mode at the end of conversion. Using this method allows very low power dissipation numbers at lower throughput rates. In this mode, the AD7472 can be operated with 3 V sup- plies at 100 kSPS, and consume an average current of just 124 µA. At 5 V supplies and 100 kSPS, the average current consumption is 171 µA. The analog input range for the part is 0 to REF IN. The +2.5 V reference is applied externally to the REF IN pin. The conver- sion rate is determined by the externally-applied clock. PRODUCT HIGHLIGHTS 1. High Throughput with Low Power Consumption. The AD7470 offers 1.75 MSPS throughput and the AD7472 offers 1.5 MSPS throughput rates with 4 mW power consumption. 2. Flexible Power/Throughput Rate Management. The conver- sion rate is determined by an externally-applied clock allow- ing the power to be reduced as the conversion rate is reduced. The part also features an auto sleep mode to maximize power efficiency at lower throughput rates. 3. No Pipeline Delay. The part features a standard successive- approximation ADC with accurate control of the sampling instant via a CONVST input and once off conversion control.

REV. A AD7470/AD7472 –2– AD7470–SPECIFICATIONS1 (VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 30 MHz @ 5 V and 24 MHz @ 3 V; TA = TMIN to TMAX 3, unless otherwise noted.) Parameter A Version 1 Units Test Conditions/Comments DYNAMIC PERFORMANCE 5 V 3 V fS = 1.75 MSPS @ 5 V, f S = 1.5 MSPS @ 3 V Signal to Noise + Distortion (SINAD) 60 60 dB min f IN = 500 kHz Sine Wave 60 60 f IN = 100 kHz Sine Wave Signal-to-Noise Ratio (SNR) 60 60 dB min f IN = 500 kHz Sine Wave 60 60 f IN = 100 kHz Sine Wave Total Harmonic Distortion (THD) –83 –83 dB typ f IN = 500 kHz Sine Wave –75 –75 dB max f IN = 100 kHz Sine Wave Peak Harmonic or Spurious Noise (SFDR) –85 –85 dB typ f IN = 500 kHz Sine Wave –75 –75 dB max f IN = 100 kHz Sine Wave Intermodulation Distortion (IMD) Second Order Terms –79 –75 dB typ f IN = 500 kHz Sine Wave –75 –75 dB max f IN = 100 kHz Sine Wave Third Order Terms –77 –75 dB typ f IN = 500 kHz Sine Wave –75 –75 dB max f IN = 100 kHz Sine Wave Aperture Delay 5 5 ns typ Aperture Jitter 15 15 ps typ Full Power Bandwidth 20 20 MHz typ DC ACCURACY fS = 1.75 MSPS @ 5 V; f S = 1.5 MSPS @ 3 V Resolution 10 10 Bits Integral Nonlinearity ±1 ±1 LSB max Differential Nonlinearity ±0.9 ±0.9 LSB max Guaranteed No Missed Codes to 10 Bits Offset Error ±2.5 ±2.5 LSB max Gain Error ±1 ±1 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF IN 0 to REF IN V DC Leakage Current ±1 ±1 µA max Input Capacitance 33 33 pF typ REFERENCE INPUT REF IN Input Voltage Range 2.5 2.5 V ±1% for Specified Performance DC Leakage Current ±1 ±1 µA max Input Capacitance 10/20 10/20 pF typ Track/Hold Mode LOGIC INPUTS Input High Voltage, V INH 2.4 2.4 V min Input Low Voltage, V INL 0.4 0.4 V max Input Current, I IN ±1 ±1 µA max Typically 10 nA, V IN = 0 V or VDD Input Capacitance, C IN 4 10 10 pF max LOGIC OUTPUTS Output High Voltage, V OH VDRIVE – 0.2 V DRIVE – 0.2 V min I SOURCE = 200 µA Output Low Voltage, V OL 0.4 0.4 V max I SINK = 200 µA Floating-State Leakage Current ±10 ±10 µA max V DD = 2.7 V to 5.25 V Floating-State Output Capacitance 10 10 pF max Output Coding Straight (Natural) Binary CONVERSION RATE Conversion Time 12 12 CLK IN Cycles (max) Track/Hold Acquisition Time 135 135 ns min Throughput Rate 1.75 1.5 MSPS max Conversion Time + Acquisition Time CLK IN of 30 MHz @ 5 V and 24 MHz @ 3 V POWER REQUIREMENTS VDD +2.7/+5.25 V min/max IDD

5 Digital I/Ps = 0 V or DV DD

Normal Mode 2.4 mA max V DD = 4.75 V to 5.25 V; fS = 1.75 MSPS; Typ 2 mA Quiescent Current 900 µA max V DD = 4.75 V to 5.25 V; f S = 1.75 MSPS Quiescent Current 800 µA max V DD = 2.7 V to 3.3 V; f S = 1.5 MSPS Sleep Mode 1 µA max CLK IN = 0 V or DV DD Power Dissipation 5 Digital I/Ps = 0 V or DV DD Normal Mode 12 mW max V DD = 5 V 4.5 mW max V DD = 3 V Sleep Mode 5 µW max V DD = 5 V; CLK IN = 0 V or DV DD 3 µW max V DD = 3 V; CLK IN = 0 V or DV DD NOTES 1Temperature ranges as follows: A Version: -40 °C to +85°C. 2The AD7470 functionally works at 2.35 V. Typical specifications @ +25 °C for SNR (100 kHz) = 59 dB; THD (100 kHz) = –84 dB; INL ± 0.8 LSB. 3The AD7470 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 20 MHz @ 5 V and 16 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA. 4Sample tested @ +25 °C to ensure compliance. 5See Power vs. Throughput Rate section. Specifications subject to change without notice.

REV. A –3– AD7470/AD7472 AD7472–SPECIFICATIONS1 (VDD = +2.7 V to +5.25 V2, REF IN = 2.5 V, fCLK IN = 26 MHz @ 5 V and 20 MHz @ 3 V; TA = TMIN to TMAX 3, unless otherwise noted.) Parameter A Version 1 B Version1 Units Test Conditions/Comments DYNAMIC PERFORMANCE 5 V3 V 5 V3 V fS = 1.5 MSPS @ 5 V, f S = 1.2 MSPS @ 3 V Signal to Noise + Distortion (SINAD) 69 69 69 69 dB typ f IN = 500 kHz Sine Wave 68 68 68 68 dB min f IN = 100 kHz Sine Wave Signal-to-Noise Ratio (SNR) 70 70 70 70 dB typ f IN = 500 kHz Sine Wave 68 68 68 68 dB min f IN = 100 kHz Sine Wave Total Harmonic Distortion (THD) –83 –78 –83 –78 dB typ f IN = 500 kHz Sine Wave –83 –84 –83 –84 dB typ f IN = 100 kHz Sine Wave –75 –75 –75 –75 dB max f IN = 100 kHz Sine Wave Peak Harmonic or Spurious Noise (SFDR) –86 –81 –86 –81 dB typ f IN = 500 kHz Sine Wave –86 –86 –86 –86 dB typ f IN = 100 kHz Sine Wave –76 –76 –76 –76 dB max f IN = 100 kHz Sine Wave Intermodulation Distortion (IMD) Second Order Terms –77 –77 –77 –77 dB typ f IN = 500 kHz Sine Wave –86 –86 –86 –86 dB typ f IN = 100 kHz Sine Wave Third Order Terms –77 –77 –77 –77 dB typ f IN = 500 kHz Sine Wave –86 –86 –86 –86 dB typ f IN = 100 kHz Sine Wave Aperture Delay 5 5 5 5 ns typ Aperture Jitter 15 15 15 15 ps typ Full Power Bandwidth 20 20 20 20 MHz typ DC ACCURACY fS = 1.5 MSPS @ 5 V; f S = 1.2 MSPS @ 3 V Resolution 12 12 12 12 Bits Integral Nonlinearity ±2 ±2 ±1 ±1 LSB max G uaranteed No Missed Codes to 11 Bits (A Version) Differential Nonlinearity ±1.8 ±1.8 ±0.9 ±0.9 LSB max G uaranteed No Missed Codes to 12 Bits (B Version) Offset Error ±10 ±10 ±10 ±10 LSB max Gain Error ±2 ±2 ±2 ±2 LSB max ANALOG INPUT Input Voltage Ranges 0 to REF IN 0 to REF IN 0 to REF IN 0 to REF IN V DC Leakage Current ±1 ±1 ±1 ±1 µA max Input Capacitance 33 33 33 33 pF typ REFERENCE INPUT REF IN Input Voltage Range 2.5 2.5 2.5 2.5 V ±1% for Specified Performance DC Leakage Current ±1 ±1 ±1 ±1 µA max Input Capacitance 10/20 10/20 10/20 10/20 pF typ Track/Hold Mode LOGIC INPUTS Input High Voltage, VINH 2.4 2.4 2.4 2.4 V min Input Low Voltage, VINL 0.4 0.4 0.4 0.4 V max Input Current, IIN ±1 ±1 ±1 ±1 µA max Typically 10 nA, V IN = 0 V or VDD Input Capacitance, CIN 4 10 10 10 10 pF max LOGIC OUTPUTS Output High Voltage, V OH VDRIVE – 0.2 V DRIVE – 0.2 V DRIVE – 0.2 V DRIVE – 0.2 V min I SOURCE = 200 µA Output Low Voltage, V OL 0.4 0.4 0.4 0.4 V max I SINK = 200 µA Floating-State Leakage Current ±10 ±10 ±10 ±10 µA max V DD = 2.7 V to 5.25 V Floating-State Output Capacitance 10 10 10 10 pF max Output Coding Straight (Natural) Binary Straight (Natural) Binary CONVERSION RATE Conversion Time 14 14 14 14 CLK IN Cycles (max) Track/Hold Acquisition Time 135 135 135 135 ns min Throughput Rate 1.5 1.2 1.5 1.2 MSPS max Conversion Time + Acquisition Time CLK IN Is 26 MHz @ 5 V and 20 MHz @ 3 V POWER REQUIREMENTS VDD +2.7/+5.25 +2.7/+5.25 V min/max IDD

5 Digital I/Ps = 0 V or DVDD

Quiescent Current 900 900 µA max V DD = 4.75 V to 5.25 V; fS = 1.5 MSPS Quiescent Current 800 800 µAV DD = 2.7 V to 3.3 V; fS = 1.2 MSPS Sleep Mode 1 1 µA max CLK IN = 0 V or DV DD Power Dissipation5 Digital I/Ps = 0 V or DVDD Normal Mode 12 12 mW max V DD = 5 V 4.5 4.5 mW max V DD = 3 V Sleep Mode 5 5 µW max V DD = 5 V; CLK IN = 0 V or DVDD 33 µW max V DD = 3 V; CLK IN = 0 V or DVDD NOTES 1Temperature ranges as follows: A and B Versions: –40 °C to +85°C. 2The AD7472 functionally works at 2.35 V. Typical specifications @ +25 °C for SNR (100 kHz) = 68 dB; THD (100 kHz) = –84 dB; INL ± 0.8 LSB. 3The AD7472 will typically maintain A-grade performance up to +125°C, with a reduced CLK of 18 MHz @ 5 V and 14 MHz @ 3 V. Typical Sleep Mode current @ +125°C is 700 nA. 4Sample tested @ +25 °C to ensure compliance. 5See Power vs. Throughput Rate section. Specifications subject to change without notice.

REV. A AD7470/AD7472 –5– CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD7470/AD7472 features proprietary ESD protection circuitry, permanent dam- age may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE ABSOLUTE MAXIMUM RATINGS 1 (TA = +25°C unless otherwise noted) Input Current to Any Pin Except Supplies Operating Temperature Range Lead Temperature, Soldering NOTES 1Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Temperature Resolution Package Model Range (Bits) Options 1 AD7470ARU –40 °C to +85°C 10 RU-24 AD7472AR –40 °C to +85°C 12 R-24 AD7472BR –40 °C to +85°C 12 R-24 AD7472ARU –40 °C to +85°C 12 RU-24 AD7472BRU –40 °C to +85°C 12 RU-24 EVAL-AD7470CB2 Evaluation Board EVAL-AD7472CB2 Evaluation Board EVAL-CONTROL BOARD3 Controller Board HSC-INTERFACE BOARD Evaluation High Speed Interface Board NOTES 1R = SOIC; RU = TSSOP. 2This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL BOARD for evaluation/demonstration p urposes. 3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. PIN CONFIGURATIONS TOP VIEW (Not to Scale) AD7470 NC = NO CONNECT DB7 DB6 DB8 DB5 (MSB) DB9 DB4 AVDD VDRIVE REF IN DV DD VIN DGND AGND DB3 CS DB2 RD DB1 CONVST DB0 (LSB) CLKIN NC BUSY NC TOP VIEW (Not to Scale) AD7472 DB9 DB8 DB10 DB7 (MSB) DB11 DB6 AVDD VDRIVE REF IN DV DD VIN DGND AGND DB5 CS DB4 RD DB3 CONVST DB2 CLKIN DB1 BUSY DB0 (LSB)

REV. A AD7470/AD7472 –6– PIN FUNCTION DESCRIPTION Pin Mnemonic Function CS Chip Select. Active low logic input used in conjunction with RD to access the conversion result. The conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to the same AND gate on the input so the signals are interchangeable. CS can be hardwired permanently low. RD Read Input. Logic Input used in conjunction with CS to access the conversion result. The conversion result is placed on the data bus following the falling edge of both CS and RD. CS and RD are both connected to same AND gate on the input so the signals are interchangeable. CS and RD can be hardwired permanently low in which case, the data bus is always active and the result of the new conversion is clocked out slightly before to the BUSY line going low. CONVST Conversion Start Input. Logic Input used to initiate conversion. The input track/hold amplifier goes from track mode to hold mode on the falling edge of CONVST and the conversion process is initiated at this point. The con- version input can be as narrow as 15 ns. If the CONVST input is kept low for the duration of conversion and is still low at the end of conversion, the part will automatically enter sleep mode. If the part enters this sleep mode, the next rising edge of CONVST wakes up the part. Wake-up time for the part is typically 1 µs. CLK IN Master Clock Input. The clock source for the conversion process is applied to this pin. Conversion time for the AD7472 takes 14 clock cycles while conversion time for the AD7470 takes 12 clock cycles. The frequency of this master clock input, therefore, determines the conversion time and achievable throughput rate. While the ADC is not converting, the Clock-In pad is in three-state and thus no clock is going through the part. BUSY BUSY Output. Logic Output indicating the status of the conversion process. The BUSY signal goes high after the falling edge of CONVST and stays high for the duration of conversion. Once conversion is complete and the con- version result is in the output register, the BUSY line returns low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisition time for the part begins when BUSY goes low. If the CONVST input is still low when BUSY goes low, the part automatically enters its sleep mode on the falling edge of BUSY. REF IN Reference Input. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. AV DD Analog Supply Voltage, +2.7 V to +5.25 V. This is the only supply voltage for all analog circuitry on the AD7470/ AD7472. The AVDD and DVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to AGND. DVDD Digital Supply Voltage, +2.7 V to +5.25 V. This is the supply voltage for all digital circuitry on the AD7470/ AD7472 apart from the output drivers. The DV DD and AVDD voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. This supply should be decoupled to DGND. AGND Analog Ground. Ground reference point for all analog circuitry on the AD7470/AD7472. All analog input signals and any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. DGND Digital Ground. This is the ground reference point for all digital circuitry on the AD7470 and AD7472. The DGND and AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart even on a transient basis. VIN Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog input presents a high dc input impedance. VDRIVE Supply Voltage for the Output Drivers, +2.7 V to +5.25 V. This voltage determines the output high voltage for the data output pins. It allows the AV DD and DVDD to operate at 5 V (and maximize the dynamic performance of the ADC) while the digital outputs can interface to 3 V logic. DB0–DB9/11 Data Bit 0 to Data Bit 9 (AD7470) and DB11 (AD7472). Parallel digital outputs that provide the conversion result for the part. These are three-state outputs that are controlled by CS and RD. The output high voltage level for these outputs is determined by the V DRIVE input.

REV. A AD7470/AD7472 –7– TERMINOLOGY Integral Nonlinearity This is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The end- points of the transfer function are zero scale, a point 1/2 LSB below the first code transition, and full scale, a point 1/2 LSB above the last code transition. Differential Nonlinearity This is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error This is the deviation of the first code transition (00 . . . 000) to Gain Error The last transition should occur at the analog value 1 1/2 LSB below the nominal full scale. The first transition is a 1/2 LSB above the low end of the scale (zero in the case of AD7470/ AD7472). The gain error is the deviation of the actual difference between the first and last code transitions from the ideal differ- ence between the first and last code transitions with offset errors removed. Track/Hold Acquisition Time The track/hold amplifier returns into track mode after the end of conversion. Track/Hold acquisition time is the time required for the output of the track/hold amplifier to reach its final value, within ± 1 LSB, after the end of conversion. Signal to (Noise + Distortion) Ratio This is the measured ratio of signal to (noise + distortion) at the output of the A/D converter. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental sig- nals up to half the sampling frequency (f S/2), excluding dc. The ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by: Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus for a 12-bit converter, this is 74 dB and for a 10-bit con- verter is 62 dB. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the rms sum of harmonics to the fundamental. For the AD7470/AD7472 it is defined as: THD dB VVVVV where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the ADC output spectrum (up to f S/2 and excluding dc) to the rms value of the fundamental. Normally, the value of this specification is deter- mined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, it will be a noise peak. Intermodulation Distortion With inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities will create distortion products at sum and difference frequencies of mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those for which neither m nor n is equal to zero. For example, the second order terms include (fa + fb) and (fa – fb), while the third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb). The AD7470/AD7472 are tested using the CCIF standard where two input frequencies near the top end of the input band- width are used. In this case, the second order terms are usually distanced in frequency from the original sine waves while the third order terms are usually at a frequency close to the input frequencies. As a result, the second and third order terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in dBs. Aperture Delay In a sample/hold, the time required after the hold command for the switch to open fully is the aperture delay. The sample is, in effect, delayed by this interval, and the hold command would have to be advanced by this amount for precise timing. Aperture Jitter Aperture jitter is the range of variation in the aperture delay. In other words, it is the uncertainty about when the sample is taken. Jitter is the result of noise which modulates the phase of the hold command. This specification establishes the ultimate timing error, hence the maximum sampling frequency for a given resolution. This error will increase as the input dV/dt increases.

status checked and, if low, the part enters sleep mode. and AD7472 only to carry out a conversion. saved. The BUSY signal can be used to gate the CLK IN pulses. Figure 13. Mode 2 Operation wake-up time as this will reduce the sampling rate of the ADC. a 5 V supply, the V DRIVE pin can be powered from a 3 V supply.

3 V parts, pushes the AD7470/AD7472 to the top bracket of

ered from a 3 V or 5 V supply. signals are related to the DV DD voltage. after power-up, as the first conversion result could be incorrect.

Figure 19. Typical DNL for 2.75 V @ +25 °C

70 AD7472 +5V

Figure 20. Typical SNR+D vs. Input Tone Figure 21. Typical THD vs. Input Tone Figure 22. Typical SNR vs. Supply Figure 23. Typical SNR @ 500 kHz Input Tone Figure 24. Typical Bandwidth

REV. A AD7470/AD7472 –16– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). C3600 –0–3/00 (rev. A) PRINTED IN U.S.A. 24-Lead SOIC (R-24) 0.0125 (0.32) 0.0091 (0.23) 8/H11543 0/H11543 0.0291 (0.74) 0.0098 (0.25)/H11547 45/H11543 0.0500 (1.27) 0.0157 (0.40) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) BSC 24 13 121 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40)PIN 1 0.6141 (15.60) 0.5985 (15.20) 24-Lead TSSOP (RU-24) 24 13 121 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30)PIN 1 0.311 (7.90) 0.303 (7.70) SEATING PLANE 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) BSC 0.0433 (1.10) MAX 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8/H11543 0/H11543