HSC-DAC-EVALCZ

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10-/12-Bit, Low Power, Broadband MxFE AD9961/AD9963 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved.

FEATURES

Dual 10-bit/12-bit, 100 MSPS ADC SNR = 67 dB, fIN = 30.1 MHz Dual 10-bit/12-bit, 170 MSPS DAC ACLR = 74 dBc 5 channels of analog auxiliary input/output Low power, <425 mW at maximum sample rates Supports full and half-duplex data interfaces Small 72-lead LFCSP lead-free package

APPLICATIONS

Picocell, femtocell basestations Medical instrumentation Ultrasound AFE Portable instrumentation Signal generators, signal analyzers GENERAL DESCRIPTION The AD9961/AD9963 are pin-compatible, 10-/12-bit, low power MxFE® converters that provide two ADC channels with sample rates of 100 MSPS and two DAC channels with sample rates to 170 MSPS. These converters are optimized for transmit and receive signal paths of communication systems requiring low power and low cost. The digital interfaces provide flexible clocking options. The transmit is configurable for 1×, 2×, 4×, and 8× interpolation. The receive path has a bypassable 2× decimating low-pass filter. The AD9961 and AD9963 have five auxiliary analog channels. Three are inputs to a 12-bit ADC. Two of these inputs can be configured as outputs by enabling 10-bit DACs. The other two channels are dedicated outputs from two independent 12-bit DACs. The high level of integrated functionality, small size, and low power dissipation of the AD9961/AD9963 make them well- suited for portable and low power applications. FUNCTIONAL BLOCK DIAGRAM DLLFILT DLL AND CLOCK DISTRIBUTION AD9961/AD9963 CLKP CLKN TXCLK TXIQ/TXnRX TXD[11:0] TRXCLK TRXIQ TRXD[11:0] RESET SDIO SCLK CS LPF LPF LPF LPF MUX TEMPERATURE SENSOR INTERNAL SERIAL PORT LOGIC REFERENCES AND BIAS LDO VREGs DATA ASSEMBLER AUX ADC AUX DAC AUX DAC AUX DAC TXIP TXIN AUXIN1 AUXIO2 AUXIO3 12-BIT DAC TXQP TXQN 12-BIT DAC RXIP RXIN 12-BIT ADC RXQP RXQN DAC12A AUX DAC DAC12B 1/2/4/8 1/2/4/8 AUXADCREF REFIO TXCML RXCML RXBIAS LDO_EN 12-BIT ADC 08801-001 Figure 1. PRODUCT HIGHLIGHTS 1. High Performance with Low Power Consumption. The DACs operate on a single 1.8 V to 3.3 V supply. Transmit path power consumption is <100 mW at 170 MSPS. Receive path power consumption is <350 mW at 100 MSPS from 1.8 V supply. Sleep and power-down modes are provided for low power idle periods. 2. High Integration. The dual transmit and dual receive data converters, five channels of auxiliary data conversion and clock generation offer complete solutions for many modem designs. 3. Flexible Digital Interface. The interface mates seamlessly to most digital baseband processors.

Rev. 0 | Page 2 of 60 TABLE OF CONTENTS

REVISION HISTORY

7/10—Revision 0: Initial Version

interpolation, unless otherwise noted. Table 1. Tx Path Specifications

decimation, unless otherwise noted. Table 2. Rx Path Specifications

TMIN to TMAX, RX33V = TXVDD = CLK33V = DRVDD = AUX33V = 3.3 V. All LDOs enabled, unless otherwise noted. Table 3. Auxiliary Converter Specifications

fCLK = 125 MHz, fDLL = 250 MHz, DAC sample rate = 125 MSPS, ADC sample rate = 62.5 MSPS, unless otherwise noted. Table 4. Power Consumption Specifications

3.3 V ONLY OPERATION (ON-CHIP REGULATORS)

Table 5. Digital Logic Level Specifications

maximizing the thermal capability of the package. Table 7. Thermal Resistance power planes, reduces the θJA.

18 SDIO

1. EXPOSED PAD MUST BE SOLDERED TO PCB.

Figure 2. AD9961 Pin Configuration Table 8. AD9961 Pin Function Descriptions 2 AUXADCREF Reference Output (Or Input) for Auxiliary ADC. 3, 4 RXQP , RXQN Differential ADC Q Inputs. The default full-scale input voltage range is 1.56 V p-p differential. 5, 11 RXGND Receive Path Ground. analog ground to improve the accuracy of the full-scale range of the Rx ADCs. 7 RX18V Output of RX18V Voltage Regulator. 9 RX18VF Output of RX18VF Voltage Regulator. 10 RXCML ADC Common-Mode Voltage Output. 12, 13 RXIN, RXIP Differential ADC I Inputs. The default full-scale input voltage range is 1.56 V p-p differential. 15 RESET Reset. Active low to reset the configuration registers to default values and reset device. 16 SCLK Clock Input for Serial Port. 17 CS Active Low Chip Select. 18 SDIO Bidirectional Data Line for Serial Port. 19, 34 DGND Digital Core Ground. 20, 33, 51 DRVDD Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V). 21 to 30 TRXD9 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode. 35 TRXIQ Output Signal Indicating from Which ADC the Output Data Is Sourced.

Rev. 0 | Page 10 of 60 Pin No. Mnemonic Description 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. 38 TXIQ/TXnRX Dual Function Pin. In half-duplex mode (TXnRX), this pin controls the direction of the TRX port. In full- duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC input data is intended. 39 to 48 TXD9 to TXD0 TxDAC Input Data. 52 DVDD18 Digital Core 1.8 V Supply. 53 DLL18V Output of DLL18V Voltage Regulator. 54 DLLFILT DLL Filter Output. 55 CLK18V Output of CLK18V Voltage Regulator. 56, 57 CLKN, CLKP Differential Input Clock. 58 CLK33V Input to CLK18V and DLL18V Voltage Regulators (1.8 V to 3.3 V). If LDOs are not being used, short Pin 58 to Pin 55. CLK33V must track TXVDD. 59, 60 TXQN, TXQP Complementary DAC Q Current Outputs. 61, 67 TXVDD Analog Supply Voltage for Tx Path (1.8 V to 3.3 V). TXVDD must track CLK33V. 62 TXCML Common-Mode Input Voltage for the I and Q Tx DACs. 63 REFIO Decoupling Point for Internal DAC 1.0 V Bandgap Reference. Use a 0.1 µF capacitor to AGND. 64 TXGND Transmit Path Ground. 65, 66 TXIP , TXIN Complementary DAC I Current Outputs. 68 DAC12B Auxiliary DAC B Output. 69 DAC12A Auxiliary DAC A Output. 70 AUXIO3 Selectable Analog Pin. Programmable to either Input 3 of the auxiliary ADC or to the auxiliary DAC10B output. 71 AUXIO2 Selectable Analog Pin. Programmable to either Input 2 of the auxiliary ADC or to the auxiliary DAC10A output. 72 AUXIN1 Input 1 of Auxiliary ADC. EPAD Thermal Pad Under Chip. This must be connected to AGND for proper chip operation. It provides both a thermal and electrical connection to the PCB.

1. EXPOSED PAD MUST BE SOLDERED TO PCB.

Figure 3. AD9963 Pin Configuration Table 9. AD9963 Pin Function Descriptions 2 AUXADCREF Reference Output (or input) for Auxiliary ADC. 3, 4 RXQP , RXQN Differential ADC Q Inputs. Full-scale input voltage range is 1.56 V p-p differential. 5, 11 RXGND Receive Path Ground. between this pin and analog ground to improve the Rx ADC full-scale accuracy. 7 RX18V Output of RX18V Voltage Regulator. 9 RX18VF Output of RX18VF Voltage Regulator. 10 RXCML ADC Common-Mode Voltage Output. 12, 13 RXIN, RXIP Differential ADC I Inputs. Full-scale input voltage range is 1.56 V p-p differential. 15 RESET Reset. Active low to reset the configuration registers to default values and reset device. 16 SCLK Clock Input for Serial Port. 17 CS Active Low Chip Select. 18 SDIO Bidirectional Data Line for Serial Port. 19, 34 DGND Digital Core Ground. 20, 33, 51 DRVDD Input/Output Pad Ring Supply Voltage (1.8 V to 3.3 V). 21 to 32 TRXD11 to TRXD0 ADC Output Data in Full Duplex Mode. ADC output data and DAC input data in half-duplex mode. 35 TRXIQ Output Signal Indicating from Which ADC the Output Data Is Sourced. 36 TRXCLK Qualifying Clock for the TRXD Bus. 37 TXCLK Qualifying Clock for the TXD Bus. It can be configured as either an input or output. duplex mode (TXIQ), this input signal indicates to which DAC, I or Q, the TxDAC Input Data is intended. 39 to 50 TXD11 to TXD0 TxDAC Input Data. 52 DVDD18 Digital Core 1.8 V Supply. 53 DLL18V Output of DLL18V Voltage Regulator.

Rev. 0 | Page 12 of 60 Pin No. Mnemonic Description 54 DLLFILT DLL Filter Output. 55 CLK18V Output of CLK18V Voltage Regulator. 56,57 CLKN, CLKP Differential Input Clock. 58 CLK33V Input to CLK18V and DLL18V Voltage Regulators (1.8 V to 3.3 V). If LDOs are not being used, short Pin 58 to Pin 55. CLK33V must track TXVDD. 59, 60 TXQN, TXQP Complementary DAC Q Current Outputs. 61, 67 TXVDD Analog Supply Voltage for Tx Path (1.8 V to 3.3V). TXVDD must track CLK33V. 62 TXCML Common-Mode Input Voltage for the I and Q Tx DACs. 63 REFIO Decoupling Point for Internal DAC 1.0 V Bandgap Reference. Use a 0.1 µF capacitor to AGND. 64 TXGND Transmit Path Ground. 65, 66 TXIP , TXIN Complementary DAC I Current Outputs. 68 DAC12B Auxiliary DAC B Output. 69 DAC12A Auxiliary DAC A Output. 70 AUXIO3 Selectable Analog Pin. Programmable to either Input 3 of the auxiliary ADC or to the auxiliary DAC10B output. 71 AUXIO2 Selectable Analog Pin. Programmable to either Input 2 of the auxiliary ADC or to the auxiliary DAC10A output. 72 AUXIN1 Input 1 of Auxiliary ADC. EPAD Thermal Pad Under Chip. This must be connected to AGND for proper chip operation. It provides both a thermal and electrical connection to the PCB.

Rev. 0 | Page 18 of 60 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error The deviation of the output current from the ideal of zero is called offset error. For TXIN, 0 mA output is expected when the inputs are all 0s. For TXIP, 0 mA output is expected when all inputs are set to 1. Gain Error The difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1 and the output when all inputs are set to 0. Output Compliance Range The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either T MIN or TMAX. For offset and gain drift, the drift is reported in parts per million of full-scale range (FSR) per degree Celsius (°C). For reference drift, the drift is reported in parts per ppm/°C. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time The time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious Free Dynamic Range (SFDR) The difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Adjacent Channel Leakage Ratio (ACLR) The ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images have the effect of wasting transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected.

Rev. 0 | Page 19 of 60 THEORY OF OPERATION The AD9961/AD9963 are targeted to cover the mixed-signal front-end needs of multiple wireless communications systems. They feature a receive path that consists of dual 10-/12-bit receive ADCs and a transmit path that consists of dual 10-/12-bit transmit DACs (TxDAC). The AD9961/AD9963 integrate additional functionality typically required in most systems, such as power scalability, Tx gain control, and clock multiplication circuitry. The AD9961/AD9963 minimize both size and power consumption to address the needs of a range of applications from the low power portable market to the high performance femto base station market. The part is provided in a 72-lead lead frame chip scale package (LFCSP) that has a footprint of only 10 mm × 10 mm. Power consumption can be optimized to suit the particular application by incorporating power-down controls, low power ADC modes, and TxDAC power scaling. In full duplex mode, the AD9961/AD9963 use two 12-bit buses, along with qualifying clock signals, to transfer Rx path data and Tx path data. These two buses support either single data rate or double data rate data transfers. The data bus, along with many other device options, is configurable through the serial port by writing internal registers. The device can also be used in a single-port, half-duplex configuration.

• SCLK (serial clock) is the input clock used to register serial control port reads and writes. Write data bits are registered on the rising edge of this clock, and read data bits are registered on the falling edge. This pin is internally pulled down by a 30 kΩ resistor to ground.
• SDIO (serial data input/output) functions as both the input and output data pin. CS (chip select bar) is an active low control that gates the read and write cycles. When GENERAL OPERATION OF SERIAL CONTROL PORT CS is high, SDIO is in a high impedance state and SCLK is disabled. This pin is internally pulled up by a 30 kΩ resistor to DRVDD. The falling edge of CS Instruction Header , in conjunction with the rising edge of SCLK, determines the start of a communication cycle. There are two parts to a communication cycle with the AD9961/ AD9963. The first part writes a 16-bit instruction word into the AD9961/AD9963, coincident with the first 16 SCLK rising edges. The instruction word provides the AD9961/AD9963 serial control ports with information regarding the data transfer, which is the second part of the communication cycle. The instruction word defines whether the upcoming data transfer is a read or a write, the number of bytes in the data transfer, and the starting register address for the first byte of the data transfer. The MSB of the instruction word is R/ W For a write, the instruction word is followed by the number of bytes of data indicated by Bit N1 to Bit N0 (see , which indicates whether the serial port transfer is a read or a write. The next two bits, N1:N0, indicate the length of the transfer in bytes. The final 13 bits are the address (A12 to A0) at which to begin the read or write operation. Table 10).

Table 10. Byte Transfer Count Bits[A12:A8] must always be 0. registered on the rising edge of SCLK. mode) is indicated by two bits (N1:N0) in the instruction byte. instruction word, where N is 1 to 3 as determined by N1:N0. decrements for each data byte of the multibyte transfer cycle. port increments for each byte of the multibyte transfer cycle.

Table 14. Configuration Register Map

Rev. 0 | Page 24 of 60 Addr Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x71 0x00 ADCCLKSEL DACCLKSEL Unused DLL_REF_EN N[3:0] 0x72 0x01 DLL_Locked DLLDIV M[4:0] 0x75 0x00 0 DLL_RESB 0 0x77 0x00 CONV_TIME[1:0] Unused AUXADC_CH[2:0] 0x78 Varies AUXADC[11:4] 0x79 Varies AUXADC[3:0] CONV_COMPL CHAN_SEL[2:0] 0x7A 0x00 AUXADC_EN AUXADC_RESB Unused AUXDIV[2:0] 0x7B 0x00 TMPSNS_EN Unused AUXREF_ADJ[2:0] Unused 0x7D 0x00 Unused RX_FSADJ[4:0] 0x7E 0x00 Unused RXTrim_EN RXTrim_Fine AUXCML_EN 0 RX_DC 0x7F 0x00 RXI_Trim[9:2] 0x80 0x00 Unused RXI_Trim[1:0] GAINCAL_ ENI 0x81 0x00 RXQ_Trim[9:2] 0x82 0x00 Unused RXQ_Trim[1:0] GAINCAL_ ENQ 0xFF 0x00 Unused Update CONFIGURATION REGISTER BIT DESCRIPTIONS Table 15. Register Name Register Address Bit(s) Parameter Function Serial Port Config 0x00 7, 0 SDIO 0: use SDIO pin as input data only. 1: use SDIO as both input and output data. 6, 1 LSB_First 0: first bit of serial data is MSB of data byte. 1: first bit of serial data is LSB of data byte. 5, 2 RESET A transition from 0 to 1 on this bit resets the device. All registers but Register 0x00 revert to their default values. ADC Address 0x05 1:0 ADDRQ, ADDRI Bits are set to determine which device on chip receives ADC specific write commands. ADC specific write commends include writes to Registers 0x0F and Register 0x10. These writes also require a rising end on the Update bit (Register 0xFF, Bit 0). 00: no ADCs are addressed. 01: I ADC is addressed. 10: Q ADC is addressed 11: both I and Q ADCs are addressed. CM Buffer Enable 0x0F 1 RXCML Enable control for the RXCML output buffer. Note that updating this bit also requires writing to Register 0x05 and Register 0xFF as described in the Sub Serial Interface Communications section. 0: RXCML pin is high impedance. 1: RXCML pin is a low impedance 1.4 V output. ADC Offset 0x10 5:0 ADC_OFFSET[5:0] Adds a dc offset to the ADC output of whichever ADC is addressed by Register 0x05. The offset applied is as follows: 011111: offset = +31 LSBs 000001: offset = +1 LSB 000000: offset = 0 LSB 111111: offset = −1 LSB 100000: offset = −32 LSBs Digital Filters 0x30 7:6 Unused 5 DEC_BP 1: bypass 2× decimator in Rx path (D0). 4 INT1_BP 1: bypass 2× Half-Band Interpolation Filter 1 (INT1). 3 INT0_BP 1: bypass 2× Half-Band Interpolation Filter 0 (INT0).

Rev. 0 | Page 25 of 60 Register Name Register Address Bit(s) Parameter Function 2 SRRC_BP 1: bypass 2× SRRC interpolation filter (SRRC). The filter chain is SRRC→INT0→INT1. If SRRC filter is enabled, the other two filters are enabled too. 1 TXCLK_EN 1: enables data clocks for transmit path. 0 RXCLK_EN 1: enables data clocks for receive path. Tx Data Interface 0x31 7 TX_SDR 0: chooses DDR clocking mode. Tx data is driven out on both edges of the TXCLK signal. 1: chooses bus rate clocking mode. Tx data is driven out on one edge of the TXCLK signal. 6 TXCKO_INV This signal inverts the phase of the transmit path output clock signal. 0: transmit path data transitions on the positive edge of the TXCLK signal. 1: transmit path data transitions on the positive edge of the TXCLK signal. 5:4 TXCLK_MD[1:0] Controls the mode of the TXCLK pin. The TXCLK pin can be configured as an input or an output. When configured as an output, it can have two possible sources, the internal TXCLK signal or the DLL output signal. 00: disabled. 01: the TXCLK pin is configured as an input. 10: the TXCLK pin is configured as an output. The source signal is the transmit path clock signal. 11: the TXCLK pin is configured as an output. The source signal is the DLL output signal. Note that the TXCLK signal may appear on either the TXCLK pin or the TRXCLK pin, depending on the mode of the device. In Half-Duplex 1- Clock mode, this signal is present on the TRXCLK pin when TX is active. In Half-Duplex 2-Clock mode and Full-Duplex mode, this signal is present on the TXCLK pin. 3 TXCKI_INV Selects which edge of the TXCLK signal samples the transmit path data. 0: TXPCLK negative edge latches transmit path data. 1: TXPCLK positive edge latches transmit path data.

2 TXIQ_HILO Data appears on the TXD bus sequentially but is loaded into the transmit

path in pairs. TXIQ_HILO selects how the TXIQ signal marks each data pair. 0: each data pair is marked by TXIQ being low then high. 1: each data pair is marked by TXIQ being high then low.

1 TX_IFIRST This bit sets the data pairing order of the I and Q samples on transmit

path. 0: selects that Q is first, followed by I. 1: selects that I is first, followed by Q. 0 TX_BNRY This bit selects the data format of the transmit path data. 0: selects twos complement. 1: selects straight binary. Rx Data Interface 0x32 7 RX_SDR 0: chooses DDR clocking mode. Rx data is driven out on both edges of the TRXCLK signal. 1: chooses bus rate clocking mode. Rx data is driven out on one edge of the TRXCLK signal.

6 Unused

5:4 RXCLK_MD[1:0] This sets the way the internal RXCLK signal in the chip is driven. 00: disabled. 01: disabled. 10: RXCLK is driven by internal Rx path clock.

Rev. 0 | Page 26 of 60 Register Name Register Address Bit(s) Parameter Function 11: RXCLK is driven by the DLL output. Note that the RXCLK signal is present on the TRXCLK pin with one exception. In Half-Duplex 1-Clock mode, the RXCLK signal is present on the TRXCLK pin when Rx is active, but the TXCLK signal appears on the TRXCLK pin when TX is active. 3 RXCLK_INV 0: uses TRxCLKIO negative edge to drive out Rxdata. 1: uses TRxCLKIO positive edge to drive out Rxdata.

2 RXIQ_HILO Data appears on the RXD bus sequentially but is sampled in the Rx path

in pairs. RXIQ_HILO selects how the RXIQ signal marks each data pair. 0: each data pair is marked by RXIQ being low then high. 1: each data pair is marked by RXIQ being high then low.

1 RX_IFIRST The Rx path I and Q ADCs sample simultaneously producing a pair of

samples. Because the RXD bus is shared, the sampled I and Q data appears on the TRXD bus sequentially. This bit determines the order of the paired samples. 0: Q appears first on Rx path. 1: I appears first on Rx path. 0 RX_BNRY 0: twos complement on Tx path. 1: straight binary on Tx path. FIFO Alignment 0x33 7 Unused 6 FIFO_INIT 1: FIFO read and write pointers are aligned after chip reset. 5 Aligned 1: FIFO read and write pointers aligned after frame input driven FIFO reset. 4 ALIGN_ACK 1: FIFO read and write pointers aligned after serial port driven FIFO reset. 3 ALIGN_REQ 1: request FIFO read and write pointers alignment via serial port. 2:0 FIFO_OFFSET[2:0] Sets the FIFO read and write pointer phase offset following FIFO reset. Normally this should be set to 4 to set the FIFFO to half full. 000 = 0. 001 = 1. 111 = 7. FIFO Status 0x34 7:0 FIFO_LVL[7:0] Indicator of the amount of valid data in the FIFO. Each one indicates a latched input sample in the FIFO. Ideally, the eight deep FIFO should be half full, indicating four latched input samples. The indicator is a thermometer code that can wrap around from LSB to MSB. Some examples follow: 00011110: indicates that FIFO is half full. The read pointer is 1 and the write pointer is 5. 10000111: indicates the FIFO is half full. The read pointer is 3 and the write pointer is 7. 00100000: indicates the FIFO has only one latched sample and is nearly empty. 01111111: indicates the FIFO has seven latched samples and is nearly over flowing. Tx Scale P 0x35 7:5 Unused 4:0 SRRC_SCALE[4:0] Value of 1.4 multiplier applied to both I and Q channels just after the SRRC filter. 00000: multiply by 0.0. 00001: multiply by 0.0625. 11111: multiply by 1.9375. Tx Scale 0 0x36 7:5 Unused 4:0 INT0_SCALE[4:0] Value of 1.4 multiplier applied to both I and Q channels just after Interpolation Filter 0.

Rev. 0 | Page 27 of 60 Register Name Register Address Bit(s) Parameter Function 00000: multiply by 0.0. 00001: multiply by 0.0625. Tx Scale 1 0x37 7:5 Unused 11111: multiply by 1.9375. 4:0 INT1_SCALE[4:0] Value of 1.4 multiplier applied to both I and Q channels just after Interpolation Filter 1. 00000: multiply by 0.0. 00001: multiply by 0.0625. 11111: multiply by 1.9375. Rx Scale 0x38 7:5 Unused 4:0 DEC_SCALE[4:0] Value of 3.2 multiplier applied to both I and Q channels just after the decimation filter. The value of the gain applied is equal to DEC_SCALE/4. 00000: multiply by 0.0. 00001: multiply by 0.25. 11111: multiply by 7.75. Clock Doubler Config 0x39 7 RXDLLRST 1: resets the Rx signal path clock doubler. 6 TXDLLRST 1: resets the Tx signal path clock doubler. 5:4 Unused 3 RXDLL_LKD The Rx clock doubler is locked. 2 TXDLL_LKD The Tx clock doubler is locked. 1 RXDBL_SEL 0: selects fixed pulse width clock doubler. 1: selects fixed duty cycle clock doubler. See Table 22 for configuration recommendations. 0 TXDBL_SEL 0: selects fixed pulse width clock doubler. 1: selects fixed duty cycle clock doubler. See Table 22 for configuration recommendations. TX Clock Doubler Config 0x3A 7:4 TX_UNLOCK[1:0] Sets the number of clock cycles for the unlock indicator. Set to 01. 3 TX_LOCK[1:0] Sets the number of clock cycles for the lock indicator. Set to 01. 2 TX_DLYOFS[1:0] Sets delay line offset of clock doubler. Set to 01. 1 TX_HYST[1:0] Sets delay line hysteresis of clock doubler. Set to 01. RX Clock Doubler Config 0x3B 7:4 RX_UNLOCK[1:0] Sets the number of clock cycles for the unlock indicator. Set to 01. 3 RX_LOCK[1:0] Sets the number of clock cycles for the lock indicator. Set to 01. 2 RX_DLYOFS[1:0] Sets delay line offset of clock doubler. Set to 01. 1 RX_HYST[1:0] Sets delay line hysteresis of clock doubler. Set to 01. Clock Doubler Config 0x3C 7:0 DBL_TAPDLY[7:0] Sets the initial tap delay of the Rx and Tx clock doublers. Set to 0x02. Data Spectral Inversion 0x3D 7:4 Unused 3 RX_INVQ 1: multiply Rxdata from QADC by −1. 2 RX_INVI 1: multiply Rxdata from IADC by −1. 1 TX_INVQ 1: multiply Txdata for QDAC by −1. 0 TX_INVI 1: multiply Txdata for IDAC by −1. Clock Doubler Pulse Width 0x3E 7:6 Unused 5:3 TX_DBLPW[2:0] Sets the pulse width of the Tx clock doubler. See Table 22 for details. 2:0 RX_DBLPW[2:0] Sets the pulse width of the Rx clock doubler. See Table 22 for details.

Rev. 0 | Page 28 of 60 Register Name Register Address Bit(s) Parameter Function Rx Data Interface 0x3F 7 Unused 6 RX_CLK 0: when SINGLERX is active, use Q side clock. 1: when SINGLERX is active, use I side clock. 5 RX_BUS 0: when SINGLERX is active, use the Q ADC. 1: when SINGLERX is active, use the I ADC. 4 SINGLERX 0: use both Rx paths. 1: use only one Rx path.

3 TXCLK_MD This bit controls the operation of the TXCLK pin when the chip is

configured in half-duplex 1-clock mode. This bit is otherwise ignored. 0: the TXCLK pin is set to a high impedance output. 1: the DLL clock output is driven onto the TXCLK pin. 2 HD_BUSCTL 0: selects SPI mode to control bus direction in half-duplex mode. 1: selects Pin mode to control bus direction in half-duplex mode. SPI bit to set Tx or Rx is Register 0x30, Bit 0. Register 0x30, Bit 1 is ignored in this case. 1 HD_CLKMD 0: selects 1-clock submode if in half-duplex mode. 1: selects 2-clock submode if in half-duplex mode.

0 FULL_DUPLEX 0: configures the digital interface for half-duplex mode (covers both 1-

clock and 2-clock submodes). 1: configures the digital interface for full-duplex mode. DAC12 Config 0x40 7 DAC12B_EN 0: powers down DAC12B. 1: enables DAC12B. 6 DAC12A_EN 0: powers down DAC12A. 1: enables DAC12A. 5 DAC12B_TOP 0: sets DAC12B range to 3.3 × VAUXDACREF. 1: sets DAC12B range to 1.8 × VAUXDACREF. 4 DAC12A_TOP 0: sets DAC12A range to 3.3 × VAUXACREF. 1: sets DAC12A range to 1.8 × VAUXDACREF. 3:2 Unused

1 AUXDAC_REF Selects where the voltage reference for all of the auxiliary DACs is

derived. 0: resistive divider from AUX33V. VAUXDACREF = VAUX33V /3.3. 1: selects the 1.0 V bandgap voltage. VAUXDACREF = 1.0 V.

0 DAC_UPDATE This bit determines which of the two data words updates all four of the

auxiliary DACs. 0: update DACs after LSB write. 1: update DACs after MSB write. DAC12A MSBs 0x41 7:0 DAC12A[11:4] DAC12A voltage control word (upper eight bits). DAC12A LSBs 0x42 7:4 Unused 3:0 DAC12A[3:0] DAC12A voltage control word (lower four bits). DAC12B MSBs 0x43 7:0 DAC12B[11:4] DAC12B voltage control word (upper eight bits). DAC12B LSBs 0x44 7:4 Unused 3:0 DAC12B[3:0] DAC12B voltage control word (lower four bits). DAC10B Config 0x45 7 DAC10B_EN 0: powers down DAC10B. 1: enables DAC10B. 6:5 Unused 4:2 DAC10B_TOP[2:0] Sets the DAC output voltage at the top range as follows: 000: 1.0 V. 001: 1.5 V.

Rev. 0 | Page 29 of 60 Register Name Register Address Bit(s) Parameter Function 010: 2.0 V. 011: 2.5 V. 100: 3.0 V. 1:0 DAC10B_RNG[1:0] The total range of the DAC extends from top-of-range, to top-of-range minus the span. The span is set as: 00: 2.0 V. 01: 1.5 V. 10: 1.0 V. 11: 0.5 V. DAC10BMSBs 0x46 7:0 DAC10B[9:2] DAC10B voltage control word (eight most significant bits). DAC10BLSBs 0x47 7:2 Unused 1:0 DAC10B[1:0] DAC10Bvoltage control word (two least significant bits). DAC10A Config 0x48 7 DAC10A_EN 0: powers down DAC10A. 1: enables DAC10A. 6:5 Unused 4:2 DAC10A_TOP[2:0] Sets the DAC output voltage at the top range as follows: 000: 1.0 V. 001: 1.5 V. 010: 2.0 V. 011: 2.5 V. 100: 3.0 V. 1:0 DAC10A_RNG[1:0] The total range of the DAC extends from top-of-range to top-of-range minus the span. The span is set as: 00: 2.0 V. 01: 1.5 V. 10: 1.0 V. 11: 0.5 V. DAC10A MSBs 0x49 7:0 DAC10A[9:2] DAC10A voltage control word (eight most significant bits). DAC10A LSBs 0x4A 7:2 Unused 1:0 DAC10A[1:0] DAC10A voltage control word (two least significant bits). TX BIST Control 0x50 7:5 Unused Unused 4 TX_PTTRN Chooses the pattern type for the BIST sequence. 0: selects checker board pattern (0xA5A, 0x5A5, 0xA5A, …). 1: selects PRN output. 3 TX_INSEL 0: selects pattern input from internal pattern generator. 1: selects pattern from the external pins of the Tx port. 2 TX_CONT 0: runs the BIST for 512 cycles. 1: runs the BIST continuously. 1 T X_START 0: keep the BIST engine in an idle state. 1: start the BIST sequence. 0 TX_BISTEN 0: disable the BIST engine. 1: enable the BIST engine. RX BIST Control 0x51 7:5 Unused 4 RX_PTTRN Chooses the pattern type for the BIST sequence. 0: selects checker board pattern (0xA5A, 0x5A5, 0xA5A, …). 1: selects PRN output. 3 RX_INSEL 0: selects pattern input from internal pattern generator. 1: selects pattern from the external pins of the Rx path. 2 RX_CONT 0: runs the BIST for 512 cycles. 1: runs the BIST continuously.

Rev. 0 | Page 30 of 60 Register Name Register Address Bit(s) Parameter Function 1 RX_START 0: keep the BIST engine in an idle state. 1: start the BIST sequence. 0 RX_BISTEN 0: disable the BIST engine. 1: enable the BIST engine. TXI Check MSB 0x52 7:0 TXI_CHK[15:8] MSB of the BIST signature value for the I side transmit path. TXI Check LSB 0x53 7:0 TXI_CHK[7:0] LSB of the BIST signature value for the I side transmit path. TXQ Check MSB 0x54 7:0 TXQ_CHK[15:8] MSB of the BIST signature value for the Q side transmit path. TXQ Check LSB 0x55 7:0 TXQ_CHK[7:0] LSB of the BIST signature value for the Q side transmit path. Version 0x5C 7:0 Chip ID[7:0] Indicates device hardware revision number. Should read back as 0x08. Power Down 0 0x60 7 DLL_EN 0: powers down DLL block. 1: enables DLL block.

6 TXDAC_PD 1: powers down the bandgap reference voltage common to both

transmit DACs and all of the auxiliary DACs. 5 TXI_SLEEP 1: turns off IDAC output current. 4 TXQ_SLEEP 1: turns off QDAC output current. 3 CLK_PD 1: turns off clock receiver. This disables all clocks on the chip except for the serial port clock.

2 RXADC_PD 1: powers down main ADC clock and the bandgap reference voltage

common to both receive ADCs. 1 RXQ_SLEEP 1: powers down the Q ADC core. 0 RXI_SLEEP 1: powers down the I ADC core. Power Down 1 0x61 7 Unused 6 DLL_LDO_PD 1: powers down LDO that supplies the DLL18V voltage rail. 5 DLLBIAS_PD 1: powers down bias sub-block inside DLL block. 4 CLK_LDO_PD 1: powers down LDO that supplies the CLK18V voltage rail. 3 RX_LDO_PD 1: powers down LDO that supplies the RX18V voltage rail. 2 RXF_LDO_PD 1: powers down LDO that supplies the RX18VF voltage rail. 1 AUXADC_PD 1: powers down AUXADC block.

0 AUX_REF_PD 1: powers down the auxiliary ADC voltage reference, allowing an external

reference to be used. LDO Status 0x62 7 DLL_LDO_STAT 1: LDO to DLL block is on (read only). 6 CLK_LDO_STAT 1: LDO to CLOCK block is on (read only). 5 RX_LDO_STAT 1: LDO to ADC blocks is on (read only). 4 RXF_LDO_STAT 1: LDO to FLASH section of ADC is on (read only). 3 DIG_LDO_STAT 1: LDO to digital core is on (read only).

2 Unused

1 Unused

0 RSET_SEL 0: selects internal 10 kΩ to generate 1 V reference. 1: selects external RSET to generate voltage reference. Output Drive 0x63 7:6 TRXD_DRV Controls the drive strength of the TRXD[11:0] pins. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. 5:4 TRXIQ_DRV Controls the drive strength of the TRXIQ pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid.

Rev. 0 | Page 31 of 60 Register Name Register Address Bit(s) Parameter Function 3:2 TRXCLK_DRV Controls the drive strength of the TRXCLK pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. 1:0 TXCLK_DRV Controls the drive strength of the TXCLK pin. 00: 4 mA output drive. 01: 8 mA output drive. 10: 12 mA output drive. 11: not valid. Clock Mode 0x66 7 TXI_DCLK 1: disables internal clock to I DAC. 6 TXQ_DCLK 1: disables internal clock to Q DAC.

5 Unused

4 RXI_DCLK 1: disables internal clock to I ADC. 3 RXQ_DCLK 1: disables internal clock to Q ADC. 2 DCS_BP 1: disables duty cycle stabilizer block. 1:0 ADCDIV[1:0] 00: selects divide by 1. Bypasses internal divider block for RXCLK. 01: selects divide by 1. Bypasses internal divider block for RXCLK. 10: selects divide by 2. 11: selects divide by 4. I DAC Gain Ctrl 0 0x68 7:6 Unused 5:0 IGAIN1[5:0] Linear in dB adjustment of the full-scale current of IDAC. Provides an adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 57 for details. I DAC Gain Ctrl 1 0x69 7:6 Unused 5:0 IGAIN2[5:0] Linear adjustment of the full-scale current of I DAC. Provides an adjustment range of approximately ±2.5% in 0.08% steps. See Figure 55 for details. I DAC Gain Ctrl 2 0x6A 7:6 Unused 5:0 IRSET[5:0] Linear adjustment of the full-scale current of I DAC. Provides an adjustment range of approximately ±20% in 0.625% steps. See Figure 55 for details. Q DAC Gain Ctrl 0 0x6B 7:6 Unused 5:0 QGAIN1[5:0] Linear in dB adjustment of the full-scale current of Q DAC. Provides an adjustment range of approximately ±6 dB in 0.25 dB steps. See Figure 56 for details. Q DAC Gain Ctrl 1 0x6C 7:6 Unused 5:0 QGAIN2[5:0] Linear adjustment of the full-scale current of Q DAC. Provides an adjustment range of approximately ±2.5% in 0.08% steps. See Figure 57 for details. Q DAC Gain Ctrl 2 0x6D 7:6 Unused 5:0 QRSET[5:0] Linear adjustment of the full-scale current of Q DAC. Provides an adjustment range of approximately ±20% in 0.625% steps. See Figure 55 for details. REFIO Adjust 0x6E 7:6 Unused 5:0 REFIO_ADJ[5:0] Adjusts the on-chip reference voltage and output at REFIO. The transmit DAC full-scale currents and the auxiliary DAC full-scale voltages are proportional to the REFIO voltage. The approximate REFIO output voltage by code is: 000000: VREF = 1.0 V. 000001: VREF = 1.00625 V. 011111: VREF = 1.19375 V.

Rev. 0 | Page 32 of 60 Register Name Register Address Bit(s) Parameter Function 100000: VREF = 0.8 V. 100001: VREF = 0.80625 V. 111111 : VREF = 0.99375 V. DLL Control 0 0x71 7 ADCCLKSEL 1: selects DLL output as the ADC sampling clock. 0: selects external clock as the ADC sampling clock. 6 DACCLKSEL 1: selects DLL output as the DAC sampling clock. 0: selects external clock as the DAC sampling clock. 4 DLL_REF_EN 1: enables the input reference clock to the DLL. 3:0 N[3:0] Sets DLL divide ratio (1 to 8) at the output of the DLL. 0000: not valid. 0001: 1. 0010: 2. 0110: 6. 0111: not valid. 1000: 8. 1001: not valid. 1111: not valid. DLL Control 1 0x72 7 DLL_Locked 1: DLL has locked to reference clock (read only). 6:5 DLLDIV[1:0] 00: DLL output is directly driven out. Divider is bypassed. 01: DLL output is directly driven out. Divider is bypassed. 10: DLL output is divided by 2. 11: DLL output is divided by 4. 4:0 M[4:0] Sets DLL multiplication factor (1 to 32). 00000: 1. 00001: 2. 11111: 32. DLL Control 2 0x75 7:4 0 Set these bits to 0. 3 DLL_RESB Reset DLL. The DLL must be reset by a low to high transition on this bit each time the DLL configuration is changed or the reference frequency is changed. 2:0 0 Set these bits to 0. Aux ADC Config 0x77 7:6 CONV_TIME[1:0] Sets the number of AUXADCCLK cycles required to perform a conversion. and Conversion Start 00: 20 AUXADCCLK cycles. 01: 22 AUXADCCLK cycles. 10: 26 AUXADCCLK cycles. 11: 34 AUXADCCLK cycles. 5:3 Unused 2:0 AUXADC_CH[2:0] Selects analog input channel to the auxiliary ADC. 000: AUXIN1, Pin 72. 001: AUXIO2, Pin 71. 010: AUXIO3, Pin 70. 011: internal VPTAT voltage. 100: internal VCMLI voltage. 101: internal VCMLQ voltage.

Rev. 0 | Page 33 of 60 Register Name Register Address Bit(s) Parameter Function 110: RXCML voltage. 111: not connected. Any write to this register initiates an ADC conversion cycle. Aux ADC MSBs 0x78 7:0 AUXADC[11:4] This is the 8 MSBs of the most recent AUXADC conversion result. Aux ADC LSBs 0x79 7:4 AUXADC[3:0] This is the 4 LSBs of the most recent AUXADC conversion result. 3 CONV_COMPL 0: indicates that the request auxiliary ADC conversion is in progress. 1: indicates that the auxiliary ADC conversion result is valid. 2:0 CHAN_SEL[2:0] Indicates the actual auxiliary ADC input channel selected for the conversion. This should match the channel that was selected in the write to Register 0x77 that initiated the conversion. Aux ADC CTRL 0 0x7A 7 AUXADC_EN 0: powers down the auxiliary ADC clock. 1: enables the auxiliary ADC clock. 6 AUXADC_RESB 1: resets the AUXADC. A transition from 0 to 1 triggers the reset. The bit should be returned to 0 after issuing the reset. 5:3 Unused 2:0 AUXDIV[2:0] Sets the frequency division ratio of the input clock driving the CLKP , CLKN pins over the AUXADCCLK. 000: 256. 001: 128. 110: 4. 111: 2. The frequency of the AUXADCCLK should be less than 10 MHz. The sample conversion rate of the AUXADC is determined by the AUXCLK rate and CONV_TIME. Aux ADC CTRL 1 0x7B 7 TEMPSNS_EN 1: enables the on-chip temperature sensor. 6:5 Unused 4:2 AUXREF_ADJ[2:0] Adjustment for tuning the internal auxiliary ADC reference voltage. 011: +18 mV. 010: +12 mV. 001: +6 mV. 000: default. 111: −6 mV. 110: −12 mV. 101: −18 mV. 100: −24 mV. 1:0 Unused ADC Full-Scale Adj 0x7D 7:5 Unused 4:0 RX_FSADJ[4:0] This parameter adjusts the full-scale input voltage range of the Rx path ADCs. The peak-to-peak input voltage range can be set as follows: 10000: 1.25 V. 10001:1.27 V. 10010: 1.29 V. 10011: 1.31 V. 11111: 1.54 V. 00000: 1.56 V. 00001: 1.58 V. 01110: 1.873 V. 01111: 1.875 V.

Rev. 0 | Page 34 of 60 Register Name Register Address Bit(s) Parameter Function Rx ADC Trim Ctrl 0x7E 7 Unused 6 RXTrim_EN 1: enables ADC gain calibration.

5 RXTrim_Fine 1: decreases the step size (increases resolution) of the gain calibration

adjustment.

4 AUXCML_EN Controls the buffers of internal bias points within each of the Rx ADCs to

allow for checking of this voltage. These voltages should read back about 0.9 V. 0: disables the buffers. 1: enables the buffers. 3:1 0 Set to 000. 0 RX_DC 0: the ADC common-mode buffer is active. This sets the ADC inputs to the desired common-mode voltage through 10 kΩ resistors to each single sided input. 1: disables the common-mode buffer. The buffer should be disabled whenever the user DC couples to the ADC inputs. IGAIN CAL MSBs 0x7F 7:0 RXI_Trim[9:2] The RXI_Trim[9:0] word is used to adjust the gain of the receive path I ADC. These bits have no effect unless the RXTrim_EN bit is set. The RXTrim_Fine bit reduces the LSB size of the calibration word by ½. IGAIN CAL LSBS 0x80 7:3 Unused 2:1 RXI_Trim[1:0] 0 GAINCAL_ENI 1: enables the gain calibration DAC for the I Rx ADC. IGAIN CAL MSBs 0x81 7:0 RXQ_Trim[9:2] The RXQ_Trim[9:0] word is used to adjust the gain of the receive path Q ADC. These bits have no effect unless the RXTrim_EN bit is set. The RXTrim_Fine bit reduces the LSB size of the calibration word by ½. IGAIN CAL LSBs 0x82 7:3 Unused 2:1 RXQ_Trim[1:0] Bottom two LSBs of RXQ_Trim described in Register 0x81 above. 0 GAINCAL_ENQ 1: enables the gain calibration DAC for the Q Rx ADC. IGAIN CAL LSBS 0xFF 7:1 Unused

0 Update Synchronously transfers ADC configuration data from the global register

set to the local ADC register set and activates the changes. A 0-to-1 transition is required to initiate the transfer. 1: transfer ADC parameters to ADC to make changes active.

Figure 46. Pass-Band Response of the Rx Path Decimation Filter

1. Write 0x01 into Register 0x05. This addresses the I channel
2. Write 0x06 into Register 0x10. This sets the IADC_Offset
3. Write 0x02 into Register 0x05. This addresses the Q
4. Write 0xFE into Register 0x10. This sets the QADC_Offset
5. Write 0x01 into Register 0xFF. This updates the data path

registers and applies the offset to the data.

1. Write 0x00 into Register 0x05. This returns the SPI to the

interpolation filters and the transmit DACs are listed in Table 1. Figure 47. Transmit Path Block Diagram

0 INT1

Figure 48. Block Diagram of Transmit Datapath the SRRC should be enabled for an interpolation factor of 8×. ratios are shown in Figure 49 through Figure 51. Figure 49. Digital Filter Transfer Function for 2× Interpolation Figure 50. Digital Filter Transfer Function for 4× Interpolation Figure 51. Digital Filter Transfer Function for 8× Interpolation

listed in Table 17 to Table 19. Table 17. Coefficient Values for INT0 Table 18. Coefficient Values for INT1 Table 19. Coefficient Values for SRRC Filter enabled. The data is then sampled by the transmit DACs. and Q samples are interleaved. input data clocking options and the clock doubler selections.

24 BITS

Figure 52. Transmit Path Data Flow and Clock Generation In Full Duplex Mode information about configuring the clock doubler, see Table 22. core, digital control logic, and full-scale output current control. effective differential current delivered to the load. Figure 53. Simplified Block Diagram of I DAC Core where DACCODE = 0 to 2N − 1. to provide programmability in the output signal level.

overview of the clocking options for each of the data converters. clock and have no relationship with the CLKP/CLKN inputs. degrade the noise and SFDR performance of the converters. sampling clock and the transmit path DAC sampling clock. which register bits are require configuration. Table 21. Clock Tree Configuration Variables Figure 65. Clock Distribution Diagram

and N can be set to values from 1 to 6 and 8. Figure 71. Recommended DLL Loop Filter 0x61, Bit 5) should be set to 0. DLL_Locked bit can be queried to verify the DLL is locked. no interpolation or decimation being used. configured according to Table 22. Table 22. Clock Doubler Configuration Guidelines 1 The DCS_BP bit should be set based on the AUXADCCLK frequency.

Table 26. TRx Bus Operation via Serial Port Table 27. Rx Bus Operation via TXnRX Pin

0 Rx High-Z

1 Tx High-Z

Figure 83. Half-Duplex Bus Turnaround, Rx to Tx Figure 84. Half-Duplex Bus Turnaround, Tx to Rx

and output compliance ranges depend on the voltage supplied. four internal signals as shown in Figure 85. Figure 85. Block Diagram of Auxiliary ADC Circuitry where R is programmed through Register 0x7A, Bits[2:0]. allowable auxiliary ADC clock speed is 10 MHz. reference. This results in an input voltage range of 0 V to 3.2 V. pin should be decoupled to AGND through a 0.22 µF capacitor. limited to sourcing less than 5 mA and sinking less than 100 µA. Table 28. Auxiliary ADC Channel Selections disabled when using this pin as an input. disabled when using this pin as an input.

011 VPTAT Voltage proportional to absolute

temperature scaled to 0.2 °K per LSB.

100 VCMLI Common mode level of the I and Q Rx

101 VCMLQ

should measure approximately 1.4 V. sources may require the 34-cycle conversion time to fully settle. recommended that the full 34-cycle conversion time be used. conversions from the same multiplexer input.

characteristic for the auxiliary ADC is shown in Figure 86.

1 LSB

Figure 86. Auxiliary ADC Transfer Function and the ADC conversion time. Figure 87. Timing Scenario for Auxiliary ADC Conversion Cycle auxiliary DACs suitable for calibration and control functions. and updated through the serial port interface. ranges, which result in 20 possible transfer functions. Figure 88. Simplified Circuit Diagram of the 10-Bit Auxiliary DAC interpreted such that ISPAN is full scale at 0x000 and zero at 0x3FF.

Figure 89. AUXDAC10 Voltage Output vs. Digital Code, VTOP = 3.0 V Figure 90. AUXDAC10 Voltage Output vs. Digital Code, VTOP = 1.5 V simplified schematic of the 12-bit auxiliary DAC.

0 TO VREF

Figure 91. Simplified Schematic of the 12-Bit Auxiliary DAC where VFS is set with the combination of bits shown in Table 29. Table 29. 12-Bit Auxiliary DAC Full-Scale Voltage Selection using the internal 1.0 V bandgap reference. Figure 92. AUXDAC12 Voltage Output vs. Digital Code

0.20 REF

0.80 MAX

0.05 MAX

0.02 NOM

8.50 REF

Figure 104. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Rev. 0 | Page 59 of 60 NOTES

Rev. 0 | Page 60 of 60 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08801-0-7/10(0)