HS-26CLV31RH RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 14
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Recommended Operating Conditions
- 2.3 Thermal Specifications
- 2.4 Electrical Specifications
- 2.5 Timing and Load Circuit Diagrams
- 3.1 Metallization Mask Layout
Features
▪ Electrically screened to SMD #5962-96663 ▪ QML qualified per MIL-PRF-38535 requirements ▪ 1.2 micron radiation hardened CMOS ▪ Extremely low stand-by current: 100µA (maximum) ▪ Operating supply range: 3.0V to 3.6V ▪ CMOS level inputs: VIH>(0.7) (VDD); VIL< (0.3) (VDD) ▪ Differential outputs: VOH > 1.8V; VOL < 0.5V ▪ High impedance outputs when disabled or powered down (VDD = 0V) ▪ Low output impedance: 10Ω or less ▪ Radiation acceptance testing - HS-26C31RH
- HDR (50-300rad (Si)/s): 300krad(Si) ▪ Radiation acceptance testing - HS-26C31EH
- HDR (50-300rad(Si)/ s): 300krad(Si)
- LDR (0.01rad(Si)/s): 50krad(Si) ▪ SEL immune to LET: 100MeV•cm2/mg ▪ Full -55°C to +125°C military temperature range ▪ Pb-free (RoHS compliant)
Applications
▪ Line transmitter for MIL-STD-1553 serial data bus ▪ Line Transmitter for RS-422 HS-26CLV31RH, HS-26CLV31EH Radiation Hardened 3.3V Quad Differential Line Drivers
FN4898 Rev.6.03 Page 3 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet 1. Pin Information
1.1 Pin Assignments
1.2 Pin Descriptions
HS1-26CLV31RH, HS1-26CLV31EH (16 LD SBDIP) CDIP2-T16- Top View HS9-26CLV31RH, HS9-26CLV31EH (16 LD Flatpack) CDFP4-F16 - Top View Pin Number Pin Name 1A I N 2A O 3A O
4 ENABLE
12 ENABLE
15 DIN
16 VDD
Figure 1. Logic Diagram Table 1. Truth Table[1]
FN4898 Rev.6.03 Page 5 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet 2. Specifications
2.1 Absolute Maximum Ratings
Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
2.2 Recommended Operating Conditions
2.3 Thermal Specifications
2.4 Electrical Specifications
Parameter Minimum Maximum Unit Supply Voltage -0.5 7.0 V DC INPUTS, E, E Voltage -0.5 V DD + 0.5 V DC Output Voltage with Power On or Off (0V -0.5 7.0 V DC DC Diode Input Current (any input) - ±20 mA DC Drain Current (any one output) - 350 mA DC VDD or Ground Current - 400 mA Junction Temperature - 175 °C Storage Temperature -65 150 °C Human Body Model (Tested per MIL-PRF-883 3015.7) - 300 V Parameter Minimum Maximum Unit Supply Voltage, V DD 3.0 3.6 V Ambient Temperature -55 +125 °C Low Input Voltage 0 0.3 V DD Maximum V High Input Voltage V DD 0.7 VDD Minimum V Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance 16Ld Flatpack Package θJA[1] 1. JA is measured with the component mounted on a high effective thermal conductivity test board (two buried 1oz copper planes) with direct attach features (package base mounted to PCB thermal land with a 10 mil gap fill material having a k of 1W/m-K. See TB379. Junction to ambient 114 °C/W θJC[2] 2. For JC, the case temperature location is the center of the package underside. Junction to case 29 °C/W Thermal Resistance 16Ld SBDIP Package θJA[1] Junction to ambient 73 °C/W θJC[2] Junction to case 24 °C/W Test Conditions: VDD = 3.0V to 3.6V; Typical values are at TA = +25°C; unless otherwise specified[1]. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 50krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.; and over a total ionizing dose of 300krad(SI) at +25°C with exposure of a high dose rate of 50krad(SI)/s to 300krad(SI)/s. Parameter Symbol Test Conditions Temp (°C) Min[2] Typ[3] Max[2] Unit High Level Output Voltage V OH VDD = 3.0V and 3.6V, IO = -20mA[4][5] Full 1.8 -- V Low Level Output Voltage V OL VDD = 3.0V and 3.6V, IO = 20mA[4][5] Full - - 0.5 V Differential Output Voltage VT, VT VDD = VIH = 3.0V, RL = R1 + R2, VIL = 0V[6] Full 1.8 -- V
FN4898 Rev.6.03 Page 6 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet Difference in Differential Output |VT| - |VT| VDD = VIH = 3.0V, RL = R1 + R2, VIL = 0V [6] Full - - 0.4 V Common Mode Output Voltage VOS, VOS VDD = VIH = 3.0V, RL = R1 + R2, VIL = 0V[6] Full - - 3.0 V Difference in Common Mode Output Voltage |VOS| - |VOS| VDD = VIH = 3.0V, RL = R1 + R2, VIL = 0V[6] Full - - 0.4 V High Level Input Voltage V IH VDD = 3.0V, 3.6V[7] Full 0.7VDD -- V Low Level Input Voltage V IL VDD = 3.0V, 3.6V[7] Full - - 0.3VDD V Standby Supply Current I DDSB VDD = 3.6V, Output = OPEN, VIN = VDD or GND Full - - 100 µA Three-state Output Leakage Current IOZ VDD = 3.6V, Force Voltage = 0V or VDD [8] Full - - ±5 µA Input Leakage I IN VDD = 3.6V, VIN = VDD or GND Full - - ±1.0 µA Output Leakage Current Power OFF IOFF VDD = 0V, VOUT = 6V, -250mV inputs = GND Full -100 - +100 µA Input Clamp Voltage V IC At -1.0mA Full - - -1.5 V At +1.0mA Full - - +1.5 V Input Capacitance C IN VDD = OPEN, f = 1MHz[9][10] Full - - 12 pF Output Capacitance C OUT VDD = OPEN, f = 1MHz[9][10] Full - - 12 pF Operating Short Circuit I OS VDD = 3.6V, VIN = VDD or GND[9][10][11] Full -30 - -150 mA On-state Resistance R ON VDD = 3.0V, VOUT = 1.5V, VIN = VDD or GND[9][10] Full - - 10 Ω Propagation Delay tPLH, tPHL VDD = 3.0V[12] Full 2 - 30 ns tPZH, tPZL -F u l l 5 - 42 ns tPHZ, tPLZ -F u l l 2 - 28 ns Output Skew t SKEW VDD = 3.0V, RL = 100Ω, CL = 40pF[12][13] Full - - 7 ns Rise and Fall Times t THL, tTLH VDD = 3.0V[12] Full 1 - 14 ns 1. All voltages are referenced to device ground unless otherwise specified. 2. Parameters with MIN and/or MAX limits are 100% tested at -55°C, +25°C and +125°C, unless otherwise specified. 4. Force / measure functions may be interchanged. 5. V IL = 0.3 VDD, VIH = 0.7VDD. 6. These test conditions are detailed in EIA specification RS-422. R1 = R2 = 50 Ω. 7. This parameter tested as inputs levels in V OL / VOH, IOZ, functional test and/or discrete voltage level. 8. The input is conditioned to have the output in the opposite state of the forcing I OZ condition. 9. These parameters are controlled through design or process parameters and are not directly tested. These parameters are charac terized upon initial design and after major design or process changes that affect these parameters. 10. Post irradiation electrical performance testing not performed for these parameters. 11. Only one output at a time may be shorted. 12. See table EIA RS-422. See Figure 2 and Figure 3. 13. Skew is defined as the difference in propagation delays between complementary outputs at the 50% point. Test Conditions: VDD = 3.0V to 3.6V; Typical values are at TA = +25°C; unless otherwise specified[1]. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 50krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.; and over a total ionizing dose of 300krad(SI) at +25°C with exposure of a high dose rate of 50krad(SI)/s to 300krad(SI)/s. (Cont.) Parameter Symbol Test Conditions Temp (°C) Min[2] Typ[3] Max[2] Unit
2.5 Timing and Load Circuit Diagrams
Figure 2. Propagation Delay Load Circuit Figure 3. Propagation Delay Timing Diagram Figure 4. Tri-State Low Load Circuit Figure 5. Tri-State Low Timing Diagram Figure 6. Tri-State High Load Circuit Figure 7. Tri-State High Timing Diagram
- Die and Assembly Characteristics
Table 2. Die and Assembly Related Information
3.1 Metallization Mask Layout
Table 3. HS-26CLV31RH, HS-26CLV31EH Pad
7 BIN 0 -4357
FN4898 Rev.6.03 Page 10 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet 4. Package Outline Drawings For the most recent package outline drawing, see K16.A. K16.A
16 Lead Ceramic Metal Seal Flatpack Package
Rev 2, 1/10 SIDE VIEW TOP VIEW SECTION A-A -D- -C- SEATING AND BASE PLANE -H- BASE LEAD FINISH METAL PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 BSC) 0.440 (11.18) 0.005 (0.13) MIN MAX 0.115 (2.92) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN 0.13 (3.30) MIN 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 LEAD FINISH adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. shall be molded to the bottom of the package to cover the leads. meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. NOTES: Dimensioning and tolerancing per ANSI Y14.5M - 1982. Controlling dimension: INCH. Index area: A notch or a pin one identification mark shall be located If a pin one identification mark is used in addition to a tab, the limits Measure dimension at all four corners. For bottom-brazed lead packages, no organic or polymeric materials Dimension shall be measured at the point of exit (beyond the
FN4898 Rev.6.03 Page 11 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet For the most recent package outline drawing, see D16.3. Ceramic Dual-In-Line Metal Seal Packages (SBDIP) Notes: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead di mensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10.Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 a9 0 o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 6 1 6 8 Rev. 0 4/94
FN4898 Rev.6.03 Page 12 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet 5. Ordering Information 6. Revision History SMD Part Number[1] 1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. Part Number[2] 2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Radiation Hardness (Total Ionizing Dose) Package Description (RoHS Compliant) Package Drawing Carrier Type Temp. Range 5962F9666302QEC HS1-26CLV31RH-8 HDR to 300krad(Si) 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9666302QXC HS9-26CLV31RH-8 16 Ld FLATPACK K16.A Tray 5962F9666302VEC HS1-26CLV31RH-Q 16 Ld SBDIP D16.3 Tube 5962F9666302VXC HS9-26CLV31RH-Q 16 Ld FLATPACK K16.A Tray 5962F9666302V9A HS0-26CLV31RH-Q [3] 3. Die product tested at T A = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the electrical performance outlined in SMD. Die N/A N/A 5962F9666302VYC HS9G-26CLV31RH-Q [4] 4. The lid of these packages are connected to the ground pin of the device. 16 Ld FLATPACK K16.A Tray N/A HS0- 26CLV31RH/SAMPLE[3][5] 5. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because they are not DLA qualified devices. N/A Die N/A N/A -55 to +125°C HS1-26CLV31RH/PROTO[5] 16 Ld SBDIP D16.3 Tube HS9-26CLV31RH/PROTO[5] 16 Ld FLATPACK K16.A Tray HS9G- 26CLV31RH/PROTO[4][5] 16 Ld FLATPACK K16.A Tray 5962F9666304VEC HS1-26CLV31EH -Q HDR to 300krad(Si) LDR to 50krad(Si) 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9666304VXC HS9-26CLV31EH-Q 16 Ld FLATPACK K16.A Tray 5962F9666304V9A HS0-26CLV31EH-Q [3] Die N/A N/A 5962F9666304VYC HS9G-26CLV31EH-Q [4] 16 Ld FLATPACK K16.A Tray Revision Date Change 6.03 May 30, 2025 Updated Figures 2 through 7.
6.02 Apr 15, 2025
Placed into the latest template. Added Pin Description table, ABS Max Ratings, Electrical Specifications, and Timing and Load Circuit Diagrams. 6.01 Aug 5, 2022 Updated Table 1.
FN4898 Rev.6.03 Page 13 May 30, 2025 HS-26CLV31RH, HS-26CLV31EH Datasheet
6.00 Oct 21, 2021
Removed Related Literature section. Added Radiation acceptance testing bullets for RH and EH parts to the features section. Updated Ordering Information table by adding carrier type and radiation testing information columns, verified part numbers in table are correct, and added Note 3 and updated Note 5. Added Truth Table. Updated the Die Characteristics information as follows: -Die thickness changed from:21mils, to:19mils. -Updated Substrate Potential (Powered Up) information.
5.00 Oct 26, 2018
Added Related Literature section. Updated Ordering Information table - added HS9G-26CLV31EH-Q part and added Notes 1 and 4. Removed part Marking column. Added Revision History. Added PODs D16.3 and K16.A Updated Disclaimer. Revision Date Change
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