5962F-9568901VXC INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically screened to SMD # 5962-95689
  • QML qualified per MIL-PRF-38535 requirements
  • 1.2 micron radiation hardened CMOS
  • L a t c h - u p f r e e
  • EIA RS-422 compatible inputs
  • CMOS compatible outputs
  • Input fail safe circuitry
  • High impedance inputs when disabled or powered down
  • Low power dissipation 138mW standby (max)
  • S i n g l e 5 V s u p p l y
  • Full -55°C to +125°C military temperature range

Applications

  • Line receiver for MIL-STD-1553 serial data bus

Ordering Information

(Note 1) INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # 5962F9568901QEC HS1-26C32RH-8 Q 5962F95 68901QEC -55 to +125 16 Ld SBDIP D16.3 5962F9568901QXC HS9-26C32RH-8 Q 5962F95 68901QXC -55 to +125 16 Ld FLATPACK K16.A 5962F9568901V9A HS0-26C32RH-Q -55 to +125 Die HS0-26C32RH/SAMPLE HS0-26C32RH/SAMPLE -55 to +125 Die 5962F9568901VEC HS1-26C32RH-Q Q 5962F95 68901VEC -55 to +125 16 Ld SBDIP D16.3 5962F9568901VXC HS9-26C32RH-Q Q 5962F95 68901VXC -55 to +125 16 Ld FLATPACK K16.A HS1-26C32RH/PROTO HS1-26C32RH/PROTO HS1- 26C 32RH /PROTO -55 to +125 16 Ld SBDIP D16.3 HS9-26C32RH/PROTO HS9-26C32RH/PROTO HS9- 26C32RH /PROTO -55 to +125 16 Ld FLATPACK K16.A 5962F9568903VEC HS1-26C32EH-Q Q 5962F95 68903VEC -55 to +125 16 Ld SBDIP D16.3 5962F9568903VXC HS9-26C32EH-Q Q 5962F95 68903VXC -55 to +125 16 Ld FLATPACK K16.A 5962F9568903V9A HS0-26C32EH-Q Q 5962F95 68903V9A -55 to +125 Die 5962F9568901VYC HS9G-26C32RH-Q (Note 2) Q 5962F95 68901VYC -55 to +125 16 Ld FLATPACK K16.A HS9G-26C32RH/PROTO HS9G-26C32RH/PROTO (Note 2) HS9G-26C32RH/PROTO -55 to +125 16 Ld FLATPACK K16.A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. The lid of these packages are connect ed to the ground pin of the device. May 28, 2013 FN3402.5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

HS-26C32RH, HS-26C32EH 2 FN3402.5 May 28, 2013 Logic Diagram Propagation Delay Timing Diagram Three-State Low Timing Diagram ENABLE ENABLE AOUTBOUTCOUT DIN DOUT DIN CIN CIN BIN BIN AIN AIN +-+-+-+- Pin Configurations HS1-26C32RH, HS1-26C32EH (16 LD SBDIP) MIL-STD-1835: CDIP2-T16 TOP VIEW HS9-26C32RH, HS9-26C32EH (16 LD FLATPACK) MIL-STD-1835: CDFP4-F16 TOP VIEW AIN AIN AOUT ENABLE COUT CIN GND CIN VDD BIN BOUT ENABLE DOUT DIN DIN BIN AIN AIN AOUT ENABLE COUT CIN CIN GND 11 6 VDD BIN BIN BOUT ENABLE DOUT DIN DIN INPUT OUTPUT -VIN +VIN = 0V VOH VOL -2.5V +2.5V VS = 50% tPLH tPHL VS INPUT VIH VSS tPZL tPLZ OUTPUT VOZ VOL VT VW

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 1. THREE-STATE LOW VOLTAGE LEVELS TABLE 2. THREE-STATE HIGH VOLTAGE LEVELS

HS-26C32RH, HS-26C32EH 4 FN3402.5 May 28, 2013 Die Characteristics DIE DIMENSIONS: 78 mils x 123 mils (1970µm x 3120µm) INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 10kÅ ± 1kÅ Top Metallization: M1: Mo/Tiw Thickness: 5800Å M2: Al/Si/Cu Thickness: 5800 Å Worst Case Current Density: <2.0 x 105A/cm2 Bond Pad Size: 110µm x 100µm Metallization Mask Layout HS-26C32RH, HS-26C32EH AIN VDD BIN AIN (2) AOUT (3) ENAB (4) COUT (5) CIN (6) (8) (9) (14) B IN (13) B OUT (12) ENAB (11) D OUT (10) D IN (1) (16) (15) (7) CIN GND DIN