HS-65647RH INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- 1.2 Micron Radiation Hardened SOS CMOS - Total Dose 3 x 105 RAD (Si) - Transient Upset >1 x 1011 RAD (Si)/s - Single Event Upset < 1 x 10-12 Errors/Bit-Day
- Latch-up Free
- LET Threshold >250 MEV/mg/cm2
- Low Standby Supply Current 10mA (Max)
- Low Operating Supply Current 100mA (2MHz)
- Fast Access Time 50ns (Max), 35ns (Typ)
- High Output Drive Capability
- Gated Input Buffers (Gated by E2)
- Six Transistor Memory Cell
- Fully Static Design
- Asynchronous Operation
- CMOS Inputs
- 5V Single Power Supply
- Military Temperature Range -55 oC to +125oC
- Industry Standard JEDEC Pinout
Description
The Intersil HS-65647RH is a fully asynchronous 8K x 8 radiation hardened static RAM. This RAM is fabricated using the Intersil 1.2 micron silicon-on-sapphire CMOS technology. This technology gives exceptional hardness to all types of radiation, including neutron fluence, total ionizing dose, high intensity ionizing dose rates, and cosmic rays. Low power operation is provided by a fully static design. Low standby power can be achieved without pull-up resistors, due to the gated input buffer design. August 1995 Spec Number 518729 File Number 2928.2 DB NA
Ordering Information
PART NUMBER TEMPERATURE RANGE PACKAGE HS1-65647RH-Q -55 oC to +125oC 28 Lead SBDIP HS1-65647RH-8 -55 oC to +125oC 28 Lead SBDIP HS1-65647RH/Proto -55 oC to +125oC 28 Lead SBDIP HS1-65647RH/Sample +25 oC 28 Lead SBDIP HS9-65647RH-Q -55 oC to +125oC 28 Lead Ceramic Flatpack HS9-65647RH-8 -55 oC to +125oC 28 Lead Ceramic Flatpack HS9-65647RH/Proto -55 oC to +125oC 28 Lead Ceramic Flatpack HS9-65647RH/Sample +25 oC 28 Lead Ceramic Flatpack HS9A-65647RH-Q -55 oC to +125oC 36 Lead Ceramic Flatpack
HS1-65647RH 28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE (SBDIP) MIL-STD-1835 CDIP2-T28 TOP VIEW HS9-65647RH 28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) MIL-STD-1835 CDFP3-F28 TOP VIEW HS9A-65647RH 36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE (FLATPACK) INTERSIL OUTLINE K36.A TOP VIEW NC A12 DQ0 DQ1 DQ2 GND VDD A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 W G VDD A11 DQ7 DQ6 DQ5 DQ4 DQ3 W G A10 DQ0 DQ1 DQ2 GND A12 NC 1 VDD A11 DQ7 DQ6 DQ5 DQ4 DQ3 W G A10 DQ0 DQ1 DQ2 GND A12 NC 1 DQ0 DQ1 DQ2 GND DQ0 DQ1 DQ2 GND Spec Number 518729
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- All voltages referenced to device GND.
- Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.)
- In order for this device to be in low power standby mode. E2 must be disabled (low).
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
- AC measurements tested at worst case VDD. Guaranteed over full operating range.
- AC measurements assume transition time≤ 5ns; input levels = 0.0V to VDD; timing reference levels = 2.0V; output load = 1 TTL equivalent
load and CL≥ 50pF, for CL > 50pF, access times are derated 0.15ns/pF.
- For timing waveforms, see Low Voltage Data Retention and Read/Write Cycles.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
- The parameters listed are controlled via design or process parameters and are not directly tested. These parameters are
characterized upon initial design release and upon design changes which would affect these characteristics.
- Applies to DIP device types only.
- Applies to Flatpack device types only.
- All measurements referenced to device GND.
TABLE 4. POST 300K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS
- DC parameters not listed in this table are tested at the +25oC pre-irradiation test limits. All AC parameters are tested at the +25oC pre-
- Typical IDDOP derating = 3mA/MHz (3mA increase in IDDOP per 1MHz increase in address frequency.)
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
TABLE 5. BURN-IN DELTA PARAMETERS (+25 oC), GROUP B, SUBGROUP 5 TABLE 6. APPLICABLE SUBGROUPS
- Alternate Group A testing in accordance with MIL-STD-883 method 5005 may be exercised.
Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) GAMMA Radiation Verification (Each Wafer) Method 1019,
2 Samples/Wafer, 0 Rejects
100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,
10 Cycles
100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In 1, Condition A or B, 72 Hours Min, +125 oC Min, Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 1) 100% Dynamic Burn-In, Condition D, 240 Hours, +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 2(T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 2) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 3) Sample - Group B, Method 5005 (Note 4) Sample - Group D, Method 5005 (Notes 4 and 5) 100% Data Package Generation (Note 6) NOTES: 1. Failures from subgroup 1, 7 and deltas are used for calculating PDA. The maximum allowable PDA = 5% with no more than 3% of the failures from subgroup 7. 2. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 3. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. separate line items for Group B Test, Group Samples, Group D Test and Group D Samples. 5. Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D Generic Data. Generic data is not guaranteed to be available and is therefore not available in all cases. 6. Data Package Contents:
- Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan- tity).
- Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
- GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
- X-Ray report and film. Includes penetrometer measurements.
- Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
- Lot Serial Number Sheet (Good units serial number and lot number).
- Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
- Group B and D attributes and/or Generic data is included when required by the P.O.
- The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 518729
Intersil Space Level Product Flow -8 GAMMA Radiation Verification (Each Wafer) Method 1019, Periodic- Wire Bond Pull Monitor, Method 2011 Periodic- Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition B 100% Temperature Cycle, Method 1010, Condition C, 100% Constant Acceleration, Method 2001, Condition per Method 5004 100% External Visual 100% Initial Electrical Test 100% Dynamic Burn-In, Condition D, 160 Hours, +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 100% PDA, Method 5004 (Note 1) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 2) Sample - Group B, Method 5005 (Note 3) Sample - Group C, Method 5005 (Notes 3 and 4) Sample - Group D, Method 5005 (Notes 3 and 4) 100% Data Package Generation (Note 5) NOTES: 1. Failures from subgroup 1, 7 are used for calculating PDA. The maximum allowable PDA = 5%. 2. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. separate line items for Group B Test, Group C Test, Group C Samples, Group D Test and Group D Samples. 4. Group C and/or Group D Generic Data, as defined by MIL-I-38535, is optional and will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group C Generic Data and/or Group D Generic Data. Generic data is not guar- anteed to be available and is therefore not available in all cases. 5. Data Package Contents:
- Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quan- tity).
- GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
- Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
- Group B, C and D attributes and/or Generic data is included when required by the P.O.
- The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative. Spec Number 518729
HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ± 10%, except R2 = 47kΩ± 10% 3. VIH: VDD± 0.5V, VIL: 0.4V± 0.4V 4. F0 = 100kHz± 10%, 50% Duty Cycle F0 = inverted F0 HS-65647RH 28 LEAD FLATPACK AND CERAMIC DIP STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ± 10% HS-65647RH 36 LEAD FLATPACK DYNAMIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ± 10%, except R2 = 4.7kΩ± 10% 3. VIH: VDD± 0.5V, VIL: 0.4V± 0.4V 4. F0 = 100kHz± 10%, 50% Duty Cycle F0 = Inverted F0 HS-65647RH 36 LEAD FLATPACK STATIC CONFIGURATION NOTES: 1. VDD = 5.5V Min 2. R = 10kΩ± 10% VDD A11 A10 DQ6 DQ7 DQ5 DQ4 DQ3 NC A12 DQ0 DQ1 DQ2 VSS VDD NC G W F13 F14 F14 F14 F10 F12 F11 F14 F14 F14 F14 F14 VDD A11 A10 DQ6 DQ7 DQ5 DQ4 DQ3 NC A12 DQ0 DQ1 DQ2 VSS VDD NC NC NC NC NC NC NC NC NC G W VSS NC W A11 A10 DQ7 DQ6 DQ5 VSS VDD NC A12 DQ0 DQ1 VDD VDD G DQ2 NC VDD VSS DQ4 DQ3 VDD VSS NC F13 F14 F14 F14 NC NC F10 F12 F11 F14 F14 F14 F14 F14 VSS NC W A11 A10 DQ7 DQ6 DQ5 VSS VDD NC A12 DQ0 DQ1 VDD VDD G DQ2 NC VDD VSS DQ4 DQ3 VDD VSS NC NC NC NC NC NC NC NC NC NC NC Spec Number 518729
HS-65647RH (8K x 8 TSOS4 SRAM) 28 LEAD CERAMIC DIP NOTES: 1. VDD = 5.5V± 0.5V R = 10kΩ± 10% 2. Group E sample size is two die/wafer. NC VDD NC A12 DQ0 DQ1 DQ2 VSS VDD A11 A10 DQ7 DQ6 DQ5 DQ4 DQ3 W G Test Patterns MARCH (II)PATTERN After a background of zeros is written, each cell (from begin- ning to end in sequence) is read, written to a one and reread. When the array is full of ones each cell (from the end to the beginning) is read, restored to a zero and reread. After this the pattern is repeated but with complemented data. MASEST PATTERN (Multiple Address Select Pattern) A checkerboard pattern is written into the memory. Then the first cell is read, then its binary address complement is read. The second cell is read and then its binary address comple- ment is read. This pattern of incrementing the address and then reading its binary address complement is repeated until the entire memory is read. This is then repeated but using a checkerboard bar pattern. GALROW PATTERN (Row Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the row. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. GALCOL PATTERN (Column Galloping Pattern) After a background of zeros is written into the memory a one is written into the first cell. It is then read alternately with each other cell in the column. The test cell is then rewritten back to a zero. The test cell is then incremented and the sequence is repeated until all cells in the memory have been used as a test cell. This is pattern then repeated but using complemented data. CHECKERBOARD PATTERN and CHECKERBOARD BAR A checkerboard is written (101010) into the memory and then the pattern is read back. This is then repeated but using complemented data. Spec Number 518729
(7) A3 (6) A4 (5) A5 (4) A6 (3) A7 (2) A12 (28) VDD (27) W (26) E2 (25) A8 (24) A9 (23) A11 (22) G NC VSS VDD NC A2 (8) A1 (9) A0 (10) DQ0 (11) DQ1 (12) DQ2 (13) VDD VSS (14) DQ3 (15) DQ4 (16) D15 (17) DQ6 (18) DQ7 (19) E (20) A10 (21) NC VDD VSS Metallization Topology DIE DIMENSIONS: 313 x 291 x 21±1mils METALLIZATION: Type: Al/Si/Cu Metal 1 Thickness: 7500 Å ± 2kÅ Metal 2 Thickness: 10kÅ ± 2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kÅ ± 1kÅ WORST CASE CURRENT DENSITY: 1.5 x 105 Amps/cm2 Spec Number 518729
NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-
0.004 H A - BM DS S
-A- -B-
0.036 H A - BM DS S
e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K36.A
36 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A - 0.138 - 3.51 - b 0.006 0.013 0.15 0.33 - b1 0.006 0.010 0.15 0.25 - c 0.004 0.011 0.10 0.28 - c1 0.004 0.008 0.10 0.20 - D 0.620 0.640 15.75 16.26 3 E 0.620 0.640 15.75 8.64 - E1 - 0.660 - 16.76 3 E2 0.470 0.490 11.94 12.45 - E3 0.030 - 0.76 - 7 e 0.025 BSC 0.64 BSC - k---- - L 0.240 0.280 6.10 7.11 - Q 0.026 0.045 0.66 1.14 8 S 1 ---- - N3 6 3 6 - Rev. 0 5/18/94 Packaging
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 HS-65647RH Spec Number