HS9403 APITECH | Alldatasheet
Document overview
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Technical content
16-Channel, 12-Bit D ata Acquisition System H S9403 D ata Converter Line
FEATURES
- M ultiplexer, instrumentation amp, S/H, A /D and control logic in a 62-pin package
- Three state output buffer
- Instrumentation amp with selectable gain ranging 1 to 1,0 0 0
- Single-ended (-16) and differential (-8) inputs
- 50 kHz minimum throughput
DESCRIPTION
The HS9403-8 and 9403-16 provide complete 12-bit data acquisition functionality in a single, 62-pin package. The 9403 includes 8- or 16-channel multiplexing, a programmable gain instrumentation amplifier, sample-hold circuit, 10V buffered reference, 12-bit 10- sec A /D and three-state output buffers. The 9403 is flexible enough to accept full-scale input ranges from ±10 mV to ±10V . Three-state output buffers allow output data to be accessed in any combination of three 4-bit bytes. Expansion to 32 single-ended or 16 differential inputs can be achieved with the addition of only 2 ICs. The 9403 is packaged in a 62-pin, hermetically sealed ceramic package. Temperature ranges available are 0ºC to 70ºC for commercial versions and –55ºC to +125ºC with M IL-STD-883C screening for military grades. CHO(+)/CHO (4) CH1(+)/CH1 (3) CH2(+)/CH2 (2) CH3(+)/CH3 (1) CH4(+)/CH4 (62) CH5(+)/CH5 (61) CH6(+)/CH6 (60) CH7(+)/CH7 (59) CH0(+)/CH8 (58) CH1(+)/CH9 (57) CH2(+)/CH10 (56) CH3(+)/CH11 (55) CH4(+)/CH12 (54) CH5(+)/CH13 (53) CH6(+)/CH14 (52) CH7(+)/CH15 (51) A 1 (12) M UX A 1 (12) A DDRESS A 1 (12) OUTPUTS A 1 (12)
16 CHA NNEL
8 CHA NNEL
S/HINSTRU. A M P
12 BIT
+ 10V REF (41) A NG SIGNA L GND A NG POW ER GND (17) DIG GND (18) +5 V DC (44) – 15 V DC (43) +15 V DCLOA D CLEA R STROBE R DELA YRA 1 RA 2 RA 4 RA 8 M UX A DDRESS INPUTS M UX ENA BLE A M P INPUT + – GA IN SETTING RESISTOR EXTERNA L HOLD CA PA CITOR S/H OUT BIPOLA R INPUT OFFSET (37) A DJUST (36) GA IN A DJUST (35) BIT 1 (M SB) (34) BIT 2 (30) BIT 5 (29) BIT 6 (28) BIT 7 (27) BIT 8 (33) BIT 3 (32) BIT 4 (31) ENA BLE (BITS 1-4) (26) ENA BLE (BITS 5-8) (25) BIT 9 (7) EOC (24) BIT 10 (23) BIT 11 (22) BIT 12 (LSB) (21) ENA BLE (BITS 9-12) (40) +10V REF OUT 165Cedar Hill Street,Marlborough,MA01752 Tel:508.485.6350 Fax: 508.485.5168 www.SpectrumMicrowave.com
(Typical @ + 25ºC and nominal power supplies unless otherwise specified) A NA LOG INPUTS HS 9403 Number of Input Channels HS 9403-8 8 Differential HS 9403-16 16 Single-Ended Input V oltage Range1 Unipolar 0 to +10V Bipolar ±10V Common M ode V oltage Range ± 11V min CM RR G=1 (1 kHz) 74 dB G=1000 (60 Hz) 110 dB Input Bias Current ±50 pA typ Bias Current Drift Doubles every 10ºC Input Offset Current ±25 pA typ. Offset Current Drift Doubles every 10ºC Input Offset V oltage ±2 mV Offset V oltage Drift (20 + 7G)µ V /ºC V oltage Noise (RTI)2 G=1 150 µ V (RM S)3 G=1000 1.6 µ V (RM S)3 Input Resistance 1012 Input Capacitance OFF Channel 10 pF ON Channel 9403-8 50 pF 9403-16 100 pF DIGITA L INPUTS Logic Levels Logic “1” +2V min,+5.5V max Logic “0” –0.3V min,+0.8V max Logic Loading Logic “1” 20 µA Logic “0” –0.2 mA STA TIC PERFORM A NCE4 No M issing Codes Guaranteed over operating temperature range Integral Linearity Error ±1/4LSB typ. ±1/2LSB max Differential Linearity Error ±1/4LSB typ. ±1/2LSB max Unipolar Offset Errors ±0.025% FSR typ. ±0.1% FSR6 max Bipolar Zero Error5 ±0.025% FSR typ. ±0.1% FSR6 max Gain Error5 ±0.025% typ. ±0.2% max + 10V REFERENCE Output V oltage + 10.000V ± 10 mV Output V oltage Drift ± 3 ppm/ºC typ, ± 8 ppm/ºC max DY NA M IC PERFORM A NCE Throughput Rate 50K Hz min S/H A cquisition Time7.11 9µsec typ. 10µsec max. A /D Conversion Time 10µsec max. A perture Delay 25 nsec typ. Sample-Hold Droop 0.1µV /µsec Feedthrough (@ 1 kHz)8.11 ±0.01% max. M UX Crosstalk (@1 kHz)11 –80dB min. Strobe Command Pulse W idth11 40 nsec min. Setup time Digital Inputs to Strobe11 50 nsec min. Hold Time Digital Inputs From Strobe1150 nsec max. ENA BLE Tri-State to V alid11 40 nsec max. V alid to Teh-State11 30 nsec max. DRIFT CHA RA CTERISTICS10 Integral Linearity ±1ppm/ºC typ, ±2 ppm/ºC max Differential Linearity ±1ppm/ºC typ, ±2 ppm/ºC max Unipolar Offset ±3ppm/ºC typ, ±7 ppm/ºC max Bipolar Zero ±3ppm/ºC typ, ±10 ppm/ºC max Gain ±8ppm/ºC typ, ±20ppm/ºC max DIGITA L OUTPUTS Logic Levels Logic " 1" 2.4V min Logic " 0" 0.4V max Logic Coding Unipolar Ranges Straight binary Bipolar Ranges Offset binary Fanout 5 TTL Loads POW ER SUPPLIES Power Supply Range ±15V ± 14.5V to ± 15.5V +5V + 4.5V to +5.5V Current Drains +15V 55 mA typ. 60 mA max –15V 60 mA typ, 68 mA max +5V 32 mA typ, 45 mA max Power Dissipation 1.4W typ.2.0W max TEM PERA TURE RA NGE Operating C-Option 0ºCto +70ºC Operating B-Option –55ºCto +125ºC Storage –65ºCto +150ºC A BSOLUTE M A XIM UM RA TINGS +V CC –0.5V to +18V –V CC + 0.5V to -18V V DD –0.3 to +7V A nalog Input Channels ±35V Digital Inputs –0.3toV DD +0.3V Notes: 1. For unity gain. 2. Referred to input. 3. M easured at output of S/H. 4. Specifications refer to entire system from M UX input to A /D output with instrumentation amplifier G= 1. 5. Initial offset and gain errors are adjustable to zero with optional external 6. FSR s full scale range. Unipolar FSR = 10V . Bipolar FSR = 20V . For a 12-bit system.1 LSB = 0.024% FSR 7. Includes M UX switching and setting time. instrumentation amp unity gain settling time and S/H acquisition time. Specified for 10V step setting to 0.01 % FSR 8. M easured at S/H output with S/H in hold mode. 9. Includes M UX address. M UX enable, dear and load inputs. 10.Unipolar 10V FSR is the basis for parts per million specifications. 11.Guaranteed but not tested. 0.150 0.250 PIN SPACING IS 0.100 INCHES ±0.005 NON- CUM ULATIVE M AXIM UM PIN DIM ENSIONS ARE 0.012 X 0.022 INCHES BOTTOM VIEW DOT ON TOP REFERENCES PIN 1 20 SPACES AT 0.100 EACH 0.035 TY P 1.250 1.400 TY P
2.300 TY P
0.160 TY P
0.0040 0.150 0.200 52 32 211 SPACES AT 0.100 EACH HS9403 Continued on next page.
NO. HS 9403-16 HS 9403-8
1 CH3 IN CH3(+)IN
2 CH2 IN CH2(+)IN
3 CH1 IN CH1(+)IN
4 CH0 IN CHO(+)IN
5 M UX ENA BLE
6 R DELA Y
7 EOC
8 STROBE
9 A 8
10 A 4 M UX A DDRESS OUT11 A 2
12 A 1
13 RA 8
14 RA 4 M UX A DDRESS IN15 RA 2
16 RA 1
17 DIGITA L GROUND
19 LOA D ENA BLE
20 CLEA R ENA BLE
21 ENA BLE (BITS 9-12)
22 BIT12 OUT(LSB)
23 BIT 11 OUT
24 BIT 10 OUT
25 BIT 9 OUT
26 ENA BLE (BITS 5.8)
27 BIT 8 OUT
28 BIT 7 OUT
29 BIT 6 OUT
30 BIT 5 OUT
31 ENA BLE (BITS 1-4)
32 BIT 4 OUT
33 BIT 3 OUT
34 BIT 2 OUT
35 BIT 1 OUT (M SB)
36 GA IN A DJ
37 OFFSET A DJ
38 BIPOLA R INPUT
39 SA M PLE/HOLD OUT
41 A NA LOG SIGNA L GROUND
42 A NA LOG POW ER GROUND
44 –15V
45 EXTERNA L HOLD CA P HIGH
46 EXTERNA L HOLD CA P LOW
47 R GA IN LOW
48 R GA IN HIGH
49 INSTRU. A M P (+) INPUT 50 INSTRU. A M P (–) INPUT
51 CH151N CH7(-)IN
52 CH14 IN CH6(-)IN
53 CH13IN CH5(-)IN
54 CH121N CH4(-)IN
55 CH11IN CH3(-)IN
56 CH10IN CH2(-)IN
57 CH9 IN CH1(-)IN
58 CH8 IN CHO(-)IN
59 CH7 IN CH7(+)lN
60 CH6 IN CH6(+)IN
61 CH5 IN CH5(+)IN
62 CH4 IN CH4(+)IN
FUNCTION PIN NO STA TE DESCRIPTION M UX ENA BLE 5 “0” Disables internal M UX “1” Enables internal M UX EOC 7 “0” Signal acquisition cycle in progress “1” A /D conversion in progress “0”to“1” Conversion complete STROBE 8 “1”to“0” Initiates acquisition and conversion of analog signal M UX A DDRESS 9-12 Output of M UX address OUT register. Straight binary coding M UX A DDRESS 13-16 Selects M UX for random IN address mode. Straight binary coding LOA D 19 “0” Random address mode initiated on falling edge of STROBE “1” Sequential address mode CLEA R 20 “0” Forces M UX address to CH0 on next falling edge of STROBE regardless of LOA D and M UX address inputs ENA BLE 21 “0” Enables three-state outputs (BITS 9-12) bits 9-12 “1” Disables three-state out puts bits 9-12 ENA BLE 26 “0” Enables three-state outputs (BITS 5-8) bits 5-8 “1” Disables three-state out puts bits 5-8 ENA BLE 31 “0” Enables three-state outputs (BITS 1-4) outputs bits 1-4 “1” Disables three-state out puts bits 1-4 FUNCTION PIN NO. DESCRIPTION R DELA Y 6 Connect external resistor to lengthen S/H acquisition time when instrumentation A M P is set for high gain (for normal operation, R DELA Y tied to +5V ). GA IN A DJUST 36 External gain adjust (optional) OFFSET A DJUST 37 External offset adjust(optional) BIPOLA R INPUT 38 For unipolar operation (0 to + 10V ). connect to pin 39 (S/H OUT). For Bipolar operation (± 10V ). connect to pin 40 (+10V REF OUT) S/H OUTPUT 39 Sample-Hold output +10V REFOUT 40 Buffered + 10V reference output EXTERNA L HOLD 45.46 A dd external polypropylene, CA PA CITOR polystyrene or teflon hold capacitor to improve S/H droop rate (optional) RGA IN 47.48 Optional gain selection point. R = 20k/(G-1). Leave open for G=1 INSTRUM ENTA TION 49.50 Use when adding additional A M P INPUTS external multiplexers for expanded single-ended or differential operation (see A pplications Information). Connect pin 50 to analog common for HS 9403-16 PIN A SSIGNM ENTS DIGITA L PIN FUNCTIONS A NA LOG PIN FUNCTIONS HS9403 Continued on next page.
Consult factory for application information. M ODEL TEM PERA TURE NUM BER RA NGE DESCRIPTION HS 9403C-8 0ºC to +70ºC 8 differential input, 12-bit. data acqusition system (DA S) HS9403C-16 0ºC to +70ºC 16 single-ended input, 12-bit, DA S HS 9403B-8 –55ºCto+125ºC 8 differential input, 12-bit, DA S M IL-STD-883C HS9403B-16 –55ºCto+125ºC 16 single-ended input, 12-bit,. DA S M IL-STD-883C HS9403C-16 FP 0ºCto+70ºC 16 single-ended input in flat pack HS9403B-16 FP –55ºCto+125ºC 16 single-ended input, in flat pack. M IL-STD-883C Specifications subject to change without notice. ORDERING INFORM A TION HS9403