HS9338 APITECH | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 3

Technical content

Complete µP Compatible 12-Bit DAC H S9338 Data Converter Line

FEATURES

  • Output ranges: 0 to +10V, ±10V.
  • Coding: binary; offset binary
  • Linearity: ±0.01%
  • Settling time: 2.5 µS
  • µP compatible
  • 28-pin package
  • CM OS, TTL compatible
  • Double buffered inputs

DESCRIPTION

HS9338 is a µP-compatible, complete 12-bit double buffered digital-to-analog converter. To enhance application flexibility, the data input registers have been configured as 3 independent 4-bit bytes. This enables the user to directly interface to 4, 8, and 12-bit data buses. HS9338 comes complete with interface control logic. The three separate byte enable inputs latch data from the bus into the appropriate primary data latches. The LDAC input transfers data from the primary latches to the DAC register. In addition to these input functions are two chip select inputs and a read/write input allowing direct memory-map configurations. All input con- trols are static to allow hardwired configurations. M SB 16 17 18 19 20 21 22 23 24 25 26 27 12 10 DATA INPUTS M IDDLE BY TE INPUT REG HIGH BY TE INPUT REG LOW BY TE INPUT REG LSB SUM JCT RANGE CONTROL LOGIC CS 4 CS 3 W R 2 HBE 6 M BE 5 LBE 7 LDAC 1 DAC REGISTER 12-BIT M DAC REFERENCE – VOUT BIPOLAR GAIN GND +15V – 15V +5V HS 9338 165CedarHill Street,Marlborough,MA01752 Tel:508.485.6350 Fax: 508.485.5168 www.SpectrumMicrowave.com

(Typical @25ºC unless otherwise noted. Power supply voltages: +15V. –15V. +5V, (±5%) M ODEL HS 9338-2 HS9338-0 DIGITA L INPUT Resolution 12 Bit Unipolar Code Binary Bipolar Code Offset Binary Logic Compatibility1 CM OS. TTL Control Logic Inputs IIH @V IH = 2.4V 20µA IIL @V IL = 0.4V –0.36mA Data Input Current5 ±1µA A NA LOG OUTPUT Scale Factor A ccuracy2 ±0.1% FSR Initial Offset2 Bipolar ±0.1% FSR max Unipolar ± 0.05% FSR max V oltage Range2 Bipolar ±10V . Unipolar 0 to +10V STA TIC PERFORM A NCE Integral Linearity3 ±0.015% FSR max ±0.050% FSR max Differential Linearity ±0.024% FSR max ±0.097% FSR max M onotonicity 12 Bits 10 Bits DY NA M IC PERFORM A NCE Full Scale Transition Settling Time 5µS max 2.5µS max Full Scale Transition Slew Rate 10V /µS min Delay to A nalog Output From Bits Input4 220nS From LDA C 220nS From CS4 or W E4 225nS STA BILITY Scale Factor 20ppm FSR Integral Linearity 1 ppm FSR max Differential Linearity 1 ppm FSR max Offset Drift Bipolar 10ppm/ºC Unipolar 5ppm/ºC M onotonicity Temperature Range 0ºC to +70ºC ± 15V POW ER SUPPLY + 15V Supply Current 12mA -15V Supply Current 10mA PSRR 0.005% /% + 5V POW ER SUPPLY + 5V Supply Current 24mA TEM PERA TURE RA NGE Operating –55ºCto +125ºC Storage –65ºCto +155ºC HS9338 Continued on next page.

1 LOAC, LOADS OAC REGISTER AND CHANGES OUTPUT

2 W R, W RITE INPUT, ACTIVATES ALL CONTROLS

3 CS2, CHIP SELECT INPUT 2

4 CS1, CHIP SELECT INPUT 1

5 M BE, M IDDLE BY TE ENABLE. D4 TO D7 6 HBE, HIGH BY TE ENABLE. D8 TO D11 7 LBE, LOW BY TE ENABLE. D0 TO D3

8 GND, GROUND, ANALOG AND DIGITAL GROUND CONNECTED INTERNALLY

9 VEE, – 15V SUPPLY

10 N.C.

11 VOUT DAC VOLTAGE OUTPUT

12 SUM JCT. SUM M ING JUNCTION OF OUTPUT OPAM P 13 BIPOLAR. CONNECTED TO SUM JCT FOR BIPOLAR OUTPUT RANGE 14 GAIN. INPUT TO ADJUST FULL SCALE OUTPUT VOLTAGE

15 VEE, -15V SUPPLY

16 D11, DATA INPUT, W EIGHT 2-1. M SB

17 D10, DATA INPUT, W EIGHT 2-2

18 09, DATA INPUT, W EIGHT 2-3 19 08, DATA INPUT, W EIGHT 2-4

20 D7, DATA INPUT, W EIGHT 2-5

21 D6, DATA INPUT, W EIGHT 2-6

22 D5, DATA INPUT, W EIGHT 2-7

23 D4, DATA INPUT, W EIGHT 2-8

24 D3, DATA INPUT, W EIGHT 2-9

25 D2, DATA INPUT, W EIGHT 2-10

26 D1, DATA INPUT, W EIGHT 2-11

27 D0, DATA INPUT, W EIGHT 2-12, LSB

28 VDD, +5V SUPPLY, CONTROL LOGIC

0.705 (17.907) M AX 0.255 (6.477) M AX 0.600 (15.240) 0.120 (3.048) PIN 1 DOT 0.17 (4.321) DIM ENSIONS inches (mm) TY P 1.540 (43.911) M AX 0.100 (2.540) TY P 0.01 (0.254) 0.020 (0.508)xBOTTOM VIEW 28 1 15 14 PACK AGE OUTLINE PIN DIAGRAM ORDERING INFORM ATION M ODEL DESCRIPTION HS 9338-2 µP DAC, 0.01% Linearity HS 9338- µP DAC, 0.05% Linearity SPECIFICATION (Continued) M ECHANICAL Case Style Ceramic NOTES: 1. Control inputs are TTL and 5V CM OS only, data inputs are fully CM OS and TTL compatible. 2. See APPLICATION NOTES for adjustment procedures. 3 Specified as “Best Straight Line”. 4. Operating the unit with the DAC Register transparent may result in output “glitches” due to logic skewing with the unit. 5. Digital Input Voltage must not exceed supply voltage or go * Same as HS 9338-2 CAUTION: ESD (Electro-Static Discharge) sensitive device. Permanent damage may occur when unconnected devices are subjected to high energy electrostatic fields. Unless otherwise noted, the voltage at any digital input should never exceed the supply voltage by more than 0.5 volts or go below –0.5 volts. HS9338