HS-26CLV32RH_13 INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 3
Technical content
Features
- Electrically screened to SMD # 5962-95689
- QML qualified per MIL-PRF-38535 requirements
- 1.2 micron radiation hardened CMOS - Single event latch-up immune IH > (0.7)(VDD); VIL < (0.3)(VDD)
- Input fail safe circuitry
- High impedance inputs when disabled or powered-down
- Full -55°C to +125°C military temperature range
- Pb-free (RoHS compliant)
Applications
- Line receiver for MIL-STD-1553 serial data bus
Ordering Information
(Note) INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # 5962F9568902QEC HS1-26CLV32RH-8 Q 5962F95 68902Q EC -55 to +125 16 Ld SBDIP D16.3 5962F9568902QXC HS9-26CLV32RH-8 Q 5962F95 68902QXC -55 to +125 16 Ld FLATPACK K16.A 5962F9568902VEC HS1-26CLV32RH-Q Q 5962F95 68902VEC -55 to +125 16 Ld SBDIP D16.3 5962F9568902VXC HS9-26CLV32RH-Q Q 5962F95 68902VXC -55 to +125 16 Ld FLATPACK K16.A 5962F9666302V9A HS0-26CLV31RH-Q -55 to +125 Die HS0-26CLV31RH/SAMPLE HS0-26CLV31RH/SAMPLE -55 to +125 Die HS1-26CLV32RH/PROTO HS1-26CLV32RH/PROTO HS1- 26CLV32RH /PROTO -55 to +125 16 Ld SBDIP D16.3 HS9-26CLV32RH/PROTO HS9-26CLV32RH/PROTO HS9- 26CLV32RH /PROTO -55 to +125 16 Ld FLATPACK K16.A 5962F9568904VEC HS1-26CLV32EH-Q Q 5962F95 68904VEC -55 to +125 16 Ld SBDIP D16.3 5962F9568904VXC HS9-26CLV32EH-Q Q 5962F95 68904VXC -55 to +125 16 Ld FLATPACK K16.A 5962F9568904V9A HS0-26CLV32EH-Q -55 to +125 Die NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. January 8, 2013 FN4907.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2000, 2008, 2009, 2012, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
HS-26CLV32RH, HS-26CLV32EH 2 FN4907.4 January 8, 2013 Logic Diagram ENABLE ENABLE AOUTBOUTCOUT DIN DOUT DIN CIN CIN BIN BIN AIN AIN +-+-+-+- Pin Configurations HS1-26CLV32RH, HS1-26CLV32EH (16 LD SBDIP) MIL-STD-1835: CDIP2-T16 TOP VIEW HS9-26CLV32RH, HS9-26CLV32EH (16 LD FLATPACK) MIL-STD-1835: CDFP4-F16 TOP VIEW NOTES: 1. For details on input output structures refer to application note AN9520. 2. For details on package dimensions refer MIL STD 1835. AIN AIN AOUT ENABLE COUT CIN GND CIN VDD BIN BOUT ENABLE DOUT DIN DIN BIN AIN AIN AOUT ENABLE COUT CIN CIN GND 11 6 VDD BIN BIN BOUT ENABLE DOUT DIN DIN
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 1. HS-26CLV32RH, HS-26CLV32EH PAD COORDINATES