HS-1135RH RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 12
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 General
- 2.2 Clamp Circuitry
- 2.3 Clamp Accuracy
- 2.4 Clamp Range
- 2.5 Recovery from Overdrive
- 7.1 Metallization Mask Layout
Features
▪ Electrically Screened to SMD #5962-96767 ▪ QML Qualified per MIL-PRF-38535 Requirements ▪ User Programmable Output Voltage Limiting ▪ Fast Overdrive Recovery: <1ns (Typ) ▪ Low Supply Current: 6.9mA (Typ) ▪ Wide -3dB Bandwidth: 360MHz (Typ) ▪ High Slew Rate: 1200V/µs (Typ) ▪ High Input Impedance: 2M (Typ) ▪ Excellent Gain Flatness (to 50MHz): 0.07dB (Typ) ▪ TID Rad Hard Assurance (RHA) testing
- HDR (50-300rad(Si)/ s): 300krad(Si) ▪ Latch Up: None (DI Technology)
Applications
▪ Flash A/D Driver ▪ Video Switching and Routing ▪ Pulse and Video Amplifiers ▪ Wideband Amplifiers ▪ RF/IF Signal Processing ▪ Imaging Systems HS-1135RH Radiation Hardened, High Speed, Low Power Current Feedback Amplifier with Programmable Output Limiting
FN4099 Rev.4.01 Page 3 May 5, 2025 HS-1135RH Datasheet 1. Pin Information
1.1 Pin Assignments
1.2 Pin Descriptions
GDIP1-T8 (CERDIP) OR CDIP2-TI (SBDIP) TOP VIEW CDFP3-F14 (FLATPACK) TOP VIEW Pin Number 8 Ld CERDIP Pin Number 14 Ld Flatpack Pin Name Description 1 1, 2, 5, 6, 8, 9, 14 NC No Connect 2 3 -IN Inverting input 3 4 +IN Non-inverting input 4 7 V- Negative power supply 51 0V L Sets the lower output clamping level. 6 11 OUT Amplifier output 7 12 V+ Positive power supply 81 3V H Sets the upper output clamping level. NC -IN +IN VH OUT V L 1NC NC -IN +IN NC NC NC V H OUT V L NC NC
2.1 General
clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs.
2.2 Clamp Circuitry
output at the final voltage. similar description applies to the symmetrical low clamp circuitry controlled by VL. an example, a unity gain circuit with VIN = 2V, VH = 1V, and RF = 510Ω would have ICLAMP = (2-1)/510Ω = 1.96mA. Note that ICC will increase by ICLAMP when the output is clamp limited. Figure 1. Simplified VH Clamp Circuitry
FN4099 Rev.4.01 Page 5 May 5, 2025 HS-1135RH Datasheet
2.3 Clamp Accuracy
The clamped output voltage will not be exactly equal to the voltage applied to VH or VL. Offset errors, mostly due to VBE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure 1, it can be seen that one component of clamp accuracy is the VBE mismatch between the QX6 transistors, and the QX5 transistors. If the transistors always ran at the same current level, there would be no VBE mismatch, and no contribution to the inaccuracy. The QX6 transistors are biased at a constant current, but as described earlier, the current through QX5 is equivalent to ICLAMP. VBE increases as ICLAMP increases, causing the clamped output voltage to increase as well. ICLAMP is a function of the overdrive level (V-IN -VOUTCLAMPED) and RF , so clamp accuracy degrades as the overdrive increases, or as RF decreases. As an example, the specified accuracy of ±60mV for a 2X overdrive with RF = 510Ω degrades to ±220mV for RF = 240Ω at the same overdrive, or to ±250mV for a 3X overdrive with RF =5 1 0Ω. Consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity.
2.4 Clamp Range
Unlike some competitor devices, both VH and VL have usable ranges that cross 0V. While VH must be more positive than VL, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the HS-1135RH could be limited to ECL output levels by setting VH = -0.8V and VL =- 1 . 8 V . VH and VL may be connected to the same voltage (GND for instance) but the result won’t be in a DC output voltage from an AC input signal. A 150 - 200mV AC signal will still be present at the output.
2.5 Recovery from Overdrive
The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (VCLAMP/AVCL) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of Unclamped Performance and Clamped Performance highlight the HS-1135RH’s sub nanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive recovery time. The appropriate propagation delays are 4.0ns for the unclamped pulse, and 4.8ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 800ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true HS-1135RH propagation delay is 500ps. 3. Use of Die in Hybrid Applications This amplifier is designed with compensation to negate the package parasitics that typically lead to instabilities. As a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. Reducing RF below the recommended values for packaged units will solve the problem. For AV = +2 the recommended starting point is 300Ω, while unity gain applications should try 400Ω.
value chip (0.1µF) capacitor works well in most cases. should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. Figure 2. Evaluation Board Schematic and Layout
FN4099 Rev.4.01 Page 7 May 5, 2025 HS-1135RH Datasheet 5. Burn-In Circuit HS-1135RH CERDIP Notes: ▪ R1 = 1kΩ, ±5% (Per Socket) ▪ R2 = 10kΩ, ±5% (Per Socket) ▪ C1 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum ▪ D1 = 1N4002 or Equivalent (Per Board) ▪ D2 = 1N4002 or Equivalent (Per Socket) ▪ V+ = +5.5V ±0.5V ▪ V- = -5.5V ±0.5V 6. Irradiation Circuit HS-1135RH CERDIP Notes: ▪ R1 = 1kΩ, ±5% ▪ R2 = 10kΩ, ±5% ▪ C1 = C2 = 0.01µF ▪ V+ = +5.0V ±0.5V ▪ V- = -5.0V ±0.5V C1 D1 D1 C1 R1 +-
- Die and Assembly Characteristics
7.1 Metallization Mask Layout
Table 1. Die and Assembly Related Information
FN4099 Rev.4.01 Page 9 May 5, 2025 HS-1135RH Datasheet 8. Package Outline Drawings The package outline drawings are located at the end of this document and are accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document. 9. Ordering Information 10. Revision History 1. SMD Ordering Note - Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. Internal Part Number[2] 2. These Pb-free Hermetic packaged products em ploy 100% Au plate -e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Radiation Hardness (Total Ionizing Dose) Package
Description
(RoHS Compliant) Package Drawing Carrier Type Temp. Range 5962F9676701VPC HS7B-1135RH-Q HDR to 300krad(Si) 8 Ld SBDIP D8.3 Tray -55 to +125°C 5962F9676701VXC HS9-1135RH-Q 8 Ld Flatpack K14.A Tray -55 to +125°C HS7B-1135RH/PROTO[3] 3. The /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and are in the same form and fit as the qualified device. These part types do not come with a Certificate of Conformance because they are not DLA qualified devices. HS7B-1135RH/PROTO N/A 8 Ld SBDIP D8.3 Tray -55 to +125°C HS9-1135RH/PROTO[3] HS9-1135RH/PROTO 8 Ld Flatpack K14.A Tray -55 to +125°C Revision Date Description
4.01 May 5, 2025
Updated POD K14.A to the latest revision; changes are as follows: -Applied latest template -Corrected typo in the mm value for dimension E1 from 7.11 to 7.37mm (i.e. the dim equivalent to E1 from the table in the previous revision) to make it equal to the 0.290 inch dim & compliant to MIL-STD-1835. -Corrected typo in the dimension of the bottom ceramic pedestal width.
4.00 May 1, 2024
Placed in the latest template. Updated Feature bullet. Added Pin Description table. Updated Ordering Information table. Updated PC Board Layout section. Added Revision history section.
Section A-A0.0015(0.04) Max0.0015(0.04) MaxBase Metal LeadFinish 0.290(7.37) Max Pin No.1ID Area 0.004HA-BD 0.036HA-BD -B--A- 0.004(0.10) the centroid of the finished lead surfaces, when solder dip or tin plate finishis applied. 9. Compliant to MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B). MinTop Vew Side View © Renesas Electronics Corporation Package Outline Drawing14 Lead Ceramic Metal Seal Flatpack Package POD Number: K14.A, Revision no: 02, Date Created: Mar 4, 2025
Hermetic Packages for Integrated Circuits Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of t he finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N8 8 8 Rev. 0 4/94
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