HS-1145RH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically Screened to SMD # 5962-96830
  • QML Qualified per MIL-PRF-38535 Requirements

Applications

  • Multiplexed Flash A/D Driver
  • RGB Multiplexers/Preamps
  • Video Switching and Routing
  • Pulse and Video Amplifiers
  • Wideband Amplifiers
  • RF/IF Signal Processing
  • Imaging Systems Pinout HS-1145RH GDIP1-T8 (CERDIP) OR CDIP2-T8 (SBDIP) TOP VIEW

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962F9683001VPA HS7-1145RH-Q -55 to 125 5962F9683001VPC HS7B-1145RH-Q -55 to 125 NC -IN +IN DISABLE OUT NC Data Sheet August 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Application Information

Although a current feedback amplifier’s bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and R All current feedback amplifiers require a feedback resistor, even for unity gain applications, and R F, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to R F. The HS-1145RH design is optimized for RF = 510Ω at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains, however, the amplifier is more stable so R F can be decreased in a trade-off of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. For a gain of +1, a resistor ( +R S) in series with +IN is required to reduce gain peaking and increase stability. Non-Inverting Input Source Impedance For best operation, the DC source impedance seen by the non-inverting input should be≥50Ω. This is especially important in inverting gain configurations where the non- inverting input would normally be connected directly to GND. DISABLE Input TTL Compatibility The HS-1145RH derives an internal GND reference for the digital circuitry as long as the power supplies are symmetrical about GND. With symmetrical supplies the digital switching threshold (V TH = (VIH + VIL)/2 = (2.0 + 0.8)/2) is 1.4V, which ensures the TTL compatibility of theDISABLE input. If asymmetrical supplies (e.g., +10V, 0V) are utilized, the switching threshold becomes: and the V IH and VIL levels will be VTH ± 0.6V, respectively. Optional GND Pad (Die Use Only) for TTL Compatibility The die version of the HS-1145RH provides the user with a GND pad for setting the disable circuitry GND reference. With symmetrical supplies the GND pad may be left unconnected, or tied directly to GND. If asymmetrical supplies (e.g., +10V, 0V) are utilized, and TTL compatibility is desired, die users must connect the GND pad to GND. With an external GND, the DISABLE input is TTL compatible regardless of supply voltage utilized. Pulse Undershoot and Asymmetrical Slew Rates The HS-1145RH utilizes a quasi-complementary output stage to achieve high output current while minimizing quiescent supply current. In this approach, a composite device replaces the traditional PNP pulldown transistor. The composite device switches modes after crossing 0V, resulting in added distortion for signals swinging below ground, and an increased undershoot on the negative portion of the output waveform (See Figures 5, 8, and 11). This undershoot isn’t present for small bipolar signals, or large positive signals. Another artifact of the composite device is asymmetrical slew rates for output signals with a negative voltage component. The slew rate degrades as the output signal crosses through 0V (See Figures 5, 8, and 11), resulting in a slower overall negative slew rate. Positive only signals have symmetrical slew rates as illustrated in the large signal positive pulse response graphs (See Figures 4, 7, and 10). PC Board Layout This amplifier’s frequency response depends greatly on the care taken in designing the PC board.The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the device’s input and output connections. Capacitance, parasitic or planned, connected to the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground at the amplifier’s inverting input (-IN), as this capacitance causes gain peaking, pulse overshoot, and if large enough, instability. To reduce this capacitance, the designer should remove the ground plane under traces connected to -IN, and keep connections to -IN as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. GAIN (ACL ) R F (Ω ) BANDWIDTH (MHz) -1 425 300 +1 510 (+R S = 510Ω ) 270 +2 510 330 +5 200 300 +10 180 130 V TH V+ V-+ HS-1145RH

  1. C1 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum
  2. D1 = 1N4002 or Equivalent (Per Board)
  3. D2 = 1N4002 or Equivalent (Per Socket)

FIGURE 27. INPUT NOISE CHARACTERISTICS FIGURE 28. SUPPLY CURRENT vs SUPPLY VOLTAGE

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 59 mils x 59 mils x 19 mils±1 mil (1500µm x 1500µm x 483µm ± 25.4µm) INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 4kÅ ±0.5kÅ Top Metallization: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ Substrate: UHF-1, Bonded Wafer, DI ASSEMBLY RELATED INFORMATION: Substrate Potential: Floating (Recommend Connection to V-) ADDITIONAL INFORMATION: Transistor Count: Metallization Mask Layout HS-1145RH NOTE: This pad is not bonded out on packaged units. Die users may set a GND reference, via this pad, to ensure the TTL compatibility of theDIS input when using asymmetrical supplies (e.g. V+ = 10V, V- = 0V). See the “Application Information” section for details. V- OPTIONAL GND (NOTE) OUT +IN -IN DISABLE HS-1145RH