HS-1135RH_09 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 9

Technical content

Features

  • Electrically Screened to SMD # 5962-96767
  • QML Qualified per MIL-PRF-38535 Requirements
  • User Programmable Output Voltage Limiting

Applications

  • Flash A/D Driver
  • Video Switching and Routing
  • Pulse and Video Amplifiers
  • Wideband Amplifiers
  • RF/IF Signal Processing
  • Imaging Systems Pinouts HS-1135RH GDIP1-T8 (CERDIP) OR CDIP2-TI (SBDIP) TOP VIEW HS-1135RH CDFP3-F14 (FLATPACK) TOP VIEW NC -IN +IN VH OUT VL 1NC NC -IN +IN NC NC NC V H OUT V L NC NC Data Sheet April 6, 2009 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN4099.3 April 6, 2009

Ordering Information

(Note) INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG DWG # 5962F9676701VPC HS7B-1135RH-Q Q5962F96 76701VPC -55 to +125 8 Ld SBDIP D8.3 5962F9676701VXC HS9-1135RH-Q Q5962F96 76701VXC -55 to +125 8 Ld Flatpack K14.A HS7B-1135RH/PROTO HS7B-1135RH/PROTO HS7B- 1135RH /PROTO -55 to +125 8 Ld SBDIP D8.3 HS9-1135RH/PROTO HS9-1135RH/PROTO HS9- 1135RH /PROTO -55 to +125 8 Ld Flatpack K14.A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. HS-1135RH

5 FN4099.3 April 6, 2009 Burn-In Circuit HS-1135RH CERDIP NOTES: 1. R 1 = 1kΩ, ±5% (Per Socket) 2. R 2 = 10kΩ, ±5% (Per Socket) 3. C 1 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum 4. D 1 = 1N4002 or Equivalent (Per Board) 5. D 2 = 1N4002 or Equivalent (Per Socket) Irradiation Circuit HS-1135RH CERDIP NOTES: 8. R 1 = 1kΩ, ±5% 9. R 2 = 10kΩ, ±5% 10. C 1 = C2 = 0.01µF C1 D1 D1 C1 R1 +- HS-1135RH

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4099.3 April 6, 2009 Die Characteristics DIE DIMENSIONS: 59 mils x 58.2 mils x 19 mils ±1 mil 1500µm x 1480µm x 483µm ±25.4µm INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 4k Å ±0.5kÅ Top Metallization: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ±0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ±0.8kÅ Substrate: UHF-1, Bonded Wafer, DI ASSEMBLY RELATED INFORMATION: Substrate Potential: Floating ADDITIONAL INFORMATION: Worst Case Current Density: < 2 x 10 5A/cm2 Transistor Count: Metallization Mask Layout HS-1135RH OUT +IN -IN VL VH HS-1135RH

7 FN4099.3 April 6, 2009 HS-1135RH Ceramic Dual-In-Line Frit Seal Packages (CERDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH bbb C A - BS c Q L A SEATING BASE D PLANE PLANE -D--A- -C- -B- α D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 A M S S ccc C A - BM DS S aaa CA - BM DS S eA F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A)

8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

A- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D- 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 -7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M- 0.0015 - 0.038 2, 3 N8 8 8 Rev. 0 4/94

8 FN4099.3 April 6, 2009 HS-1135RH Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)

8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D- 0.405 - 10.29 - E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 -6 S2 0.005 - 0.13 -7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M- 0.0015 - 0.038 2 N8 8 8 Rev. 0 4/94

9 FN4099.3 April 6, 2009 HS-1135RH Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from t he body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D- 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E1 - 0.290 - 7.11 3 E2 0.125 - 3.18 -- E3 0.030 - 0.76 -7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 -6 M- 0.0015 - 0.04 - N1 4 1 4- Rev. 0 5/18/94