HSP45116883 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
  • NCO and CMAC on One Chip
  • 15MHz and 25.6MHz Versions
  • 32-Bit Frequency Control
  • 16-Bit Phase Modulation
  • 16-Bit CMAC
  • 0.006Hz Tuning Resolution at 25.6MHz
  • Spurious Frequency Components < -90dBc
  • Fully Static CMOS

Applications

  • Frequency Synthesis
  • Modulation - AM, FM, PSK, FSK, QAM
  • Demodulation, PLL
  • Phase Shifter
  • Polar to Cartesian Conversions Block Diagram

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HSP45116GM-15/883 -55 to 125 145 Ld PGA G145.A HS45116GM-25/883 -55 to 125 145 Ld PGA G145.A PHASE/ FREQUENCY CONTROL SECTION SINE/ COSINE SECTION CMAC SINE/ COSINE ARGUMENT SIN COS VECTOR INPUT VECTOR OUTPUT RI RI MICROPROCESSOR INTERFACE INDIVIDUAL CONTROL SIGNALS Data Sheet May 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved

device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

  1. θJA is measured with the component mounted on an evaluation PC board in free air.

TABLE 1. DC ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. Interchanging of force and sense conditions is permitted.
  2. Operating Supply Current is proportional to frequency, typical rating is 10mA/MHz.
  3. Tested as follows: f = 1MHz, V
  4. Output per test load circuit with switch open and C L = 40pF.

TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. Applicable only when outputs are being monitored and ENCFREG , ENPHREG, or ENTIREG is active.
  2. Transition is measured at ±200mV from steady state voltage, output loading per test load circuit, with switch closed and C L = 40pF.

TABLE 3. ELECTRICAL PERFORMANCE SPECIFICATIONS

  1. The parameters in Table 3 are controlled via design or process parameters and not directly tested. Characterized upon initial design and after

major process and/or design changes.

  1. Loading is as specified in the test load circuit with C L = 40pF.

TABLE 4. APPLICABLE SUBGROUPS TABLE 2. ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Burn-In Circuit

145 PIN PGA

A B C D E F G H J K L M N P Q A B C D E F G H J K L M N P Q 123456789 1 0 1 1 1 2 1 3 1 4 1 5 123456789 1 0 1 1 1 2 1 3 1 4 1 5 GND VCC VCC VCC GND GND GND GND VCC VCC GND VCC GND IMIN10IMIN7IMIN5 IMIN13 IMIN12IMIN6IMIN3IMIN2 INDEX RIN7 RIN11 RIN12 RIN9 RIN8 RIN6 RIN5 RIN3 RIN1 RIN4 ACC CLK AD1 C15 C10 MOD0ENOF REG AD0 C14 C13 C8 C2 PACO RO1 RO5 RO8 RO9 RO14 IO0 IO3 RO18 IO2 IO10 IO1IO4 RO19 RO17 RO16 RO15 RO13 RO11 RO12 RO10 RO7 RO4 RO6RO2 DET1 RO3 OEREXT OEI RO0 OEIEXT DET0 C3 C1 OER C5 C4 C0 TICO PACI BINFMT PEAKENPH REG MOD1 LOAD CLROFR ENI ENCF REG ENTIREG WR CS MODPI /2PI C7C11C12 SH1 RBYTILD RIN0RIN2 SH0 PMSEL ENPHAC IMIN17 IMIN18 IO17 IO13 IO9 IO6 IO5IO7IO8IO11IO14IO16IO19IMIN14 IO18 IO15 IO12VCC GND V CCIMIN16IMIN4 IMIN8 IMIN9 IMIN11 IMIN15 IMIN 1 RIN18RIN15 RIN17RIN13 IMIN0 RIN10 RIN14 RIN16 OUT- MUX0 OUT- MUX1 HSP45116/883

DIE DIMENSIONS: 350 mils x 353 mils x 19 ± 1mils METALLIZATION: Type: Si-Al, or Si-Al-Cu Thickness: 8kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å WORST CASE DENSITY: 1.6 x 105A/cm2 Burn-in Circuit PGA PIN PIN NAME BURN-IN- SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL PGA PIN PIN NAME BURN-IN SIGNAL D3 IMIN(0) F4 Q3 ENPHAC F1 K14 RO(2) V CC/2 A10 IO(18) V CC/2 C2 RIN(18) F9 P5 ENTIREG F4 L15 RO(3) V CC/2 B8 IO(19) V CC/2 D2 RIN(17) F8 Q4 ENI F1 J14 RO(4) V CC/2 C8 IMIN(18) F9 E3 RIN(16) F7 N6 MODPI/2PI F16 J13 RO(5) V CC/2 C7 IMIN(17) F8 C1 RIN(15) F6 P6 CS F2 K15 RO(6) V CC/2 A7 IMIN(16) F7 E2 RIN(14) F5 Q5 CLK F0 H14 RO(7) V CC/2 A6 IMIN(15) F6 D1 RIN(13) F4 P7 AD(1) F4 H13 RO(8) V CC/2 B7 IMIN(14) F5 F3 RIN(12) F16 N7 AD(0) F3 G13 RO(9) V CC/2 B6 IMIN(13) F4 F2 RIN(11) F15 Q6 WR F1 G15 RO(10) V CC/2 C6 IMIN(12 F16 E1 RIN(10) F14 P8 C(15) GND F15 RO(11) V CC/2 A5 IMIN(11) F15 G2 RIN(9) F13 N8 C(14) GND G14 RO(12) V CC/2 B5 IMIN(10) F14 G3 RIN(8) F12 N9 C(13) GND F14 RO(13) V CC/2 A4 IMIN(9) F13 F1 RIN(7) F11 Q9 C(12) GND F13 RO(14) V CC/2 A3 IMIN(8) F12 H2 RIN(6) F10 Q10 C(11) GND E15 RO(15) V CC/2 B4 IMIN(7) F11 H3 RIN(5) F9 P9 C(10) GND E14 RO(16) V CC/2 C5 IMIN(6) F10 J3 RIN(4) F8 P10 C(9) GND D15 RO(17) V CC/2 B3 IMIN(5) F9 J1 RIN(3) F7 N10 C(8) GND C15 RO(18) V CC/2 A2 IMIN(4) F8 K1 RIN(2) F6 Q11 C(7) GND D14 RO(19) V CC/2 C4 IMIN(3) F7 J2 RIN(1) F5 P11 C(6) GND E13 IO(0) V CC/2 C3 IMIN(2) F6 K2 RIN(0) F4 Q12 C(5) GND C14 IO(1) V CC/2 B2 IMIN(1) F5 K3 SH(1) F3 Q13 C(4) GND B15 IO(2) V CC/2 A1 VC None L1 SH(0) F2 P12 C(3) GND D13 IO(3) V CC/2 A9 V CC VCC L2 ACC F4 N11 C(2) GND C13 IO(4) V CC/2 A15 V CC None M1 ENPHREG F16 P13 C(1) GND B14 IO(5) V CC/2 G1 V CC VCC N1 ENOFREG F4 Q14 C(0) V CC C12 IO(6) V CC/2 J15 V CC VCC M2 PEAK F8 N12 OUT- MUX(1) F11 B13 IO(7) V CC/2 Q1 V CC None L3 RBYTILD F16 N13 OUT- MUX(0) F10 B12 IO(8) V CC/2 Q7 V CC VCC N2 BINFMT F4 P14 OER F0 C11 IO(9) V CC/2 Q15 V CC None P1 TICO VCC/2 M13 OEREXT F0 A13 IO(10) V CC/2 A8 GND GND M3 MOD(1) GND N14 OEIEXT F0 B11 IO(11) V CC/2 A14 GND None N3 MOD(0) GND M14 OEI F0 A12 IO(12) V CC/2 B1 GND None P2 PACI F4 L13 PACO VCC/2 C10 IO(13) V CC/2 H1 GND GND N4 LOAD F15 N15 DET0 V CC/2 B10 IO(14) V CC/2 H15 GND GND P3 PMSEL F1 L14 DET1 V CC/2 A11 IO(15) V CC/2 P15 GND None P4 CLROFR F4 M15 RO(0) V CC/2 B9 IO(16) V CC/2 Q2 GND None N5 ENCFREG F4 K13 RO(1) V CC/2 C9 IO(17) V CC/2 Q8 GND GND NOTE: 11. 47k Ω ±20%) resistor connected to all pins except V CC and GND. 14. Input Voltage limits: V IL = 0.8V max, VIH = 4.5V ±10%. HSP45116/883