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Document overview

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Technical content

Features

  • Electrically screened to DLA SMD# 5962-99560
  • QML qualified per MIL-PRF-38535 requirements
  • L a t c h - u p i m m u n e
  • R a d i a t i o n e n v i r o n m e n t *Limit established by characterization
  • Matched rise and fall times (CL = 4300pF). . 75ns (maximum)
  • Consistent delay times with V CC changes
  • L o w p o w e r c o n s u m p t i o n - 40mW with inputs high - 20mW with inputs low

Applications

  • Switching power supplies
  • D C / D C c o n v e r t e r s
  • M o t o r c o n t r o l l e r s

TABLE 1. HS4424 PRODUCT FAMILY SPECIFIC UVLO Vth FIGURE 1. TYPICAL APPLICATION FIGURE 2. UNDERVOLTAGE LOCKOUT vs TEMPERATURE CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

FIGURE 3. CIRCUIT 1 FIGURE 4. CIRCUIT 2

HS-4424DRH, HS4424DEH 3 FN8747.2 October 15, 2015 Submit Document Feedback Functional Block Diagram

Ordering Information

(Note 2) PART NUMBER (Note 1) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F9956005V9A HS0-4424DRH-Q -55 to +125 DIE HS0-4424DRH/SAMPLE HS0-4424DRH/SAMPLE -55 to +125 DIE SAMPLE 5962F9956005VXC HS9-4424DRH-Q -55 to +125 16 Ld Flatpack K16.A HS9-4424DRH/PROTO HS9-4424DRH/PROTO -55 to +125 16 Ld Flatpack K16.A 5962F9956006V9A HS0-4424DEH-Q -55 to +125 DIE 5962F9956006VXC HS9-4424DEH-Q -55 to +125 16 Ld Flatpack K16.A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering. Control LogicLevel Shifter & UVLO & UVLO OUT A OUT B VCC IN A GND A VCC OUT A Control LogicLevel Shifter IN B OUT B GND B OUT A OUT A OUT B OUT B VCC IN A GND A VCC IN B GND B LEVEL SHIFTER LEVEL SHIFTER CONTROL AND LOGIC UVLO CONTROL AND LOGIC UVLO FIGURE 5. BLOCK DIAGRAM

HS-4424DRH, HS4424DEH 4 FN8747.2 October 15, 2015 Submit Document Feedback Absolute Maximum Ratings Thermal Information ESD Rating Thermal Resistance (Typical) JA (°C/W) JC (°C/W) Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379 for details. 4. For JC, the “case temp” location is the center of the package underside. Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 5)T Y P MAX (Note 5)U N I T VSUPPLY Supply Voltage Range 81 8 V ICCSB LOW 18V Bias Current V S = 18V, Inputs = 0V 3.5 mA VS = 18V, Inputs = 0V 4 mA VS = 18V, Inputs = 0V, post radiation 4 mA ICCSB HIGH 18V Bias Current V S, Inputs = 18V 3.5 mA VS, Inputs = 18V 4 mA VS, Inputs = 18V, post radiation 4 mA ICCSB LOW 8V Bias Current V S = 8V, Inputs = 0V 3.5 mA VS = 8V, Inputs = 0V 4 mA VS = 8V, Inputs = 0V, post radiation 4 mA ICCSB HIGH 8V Bias Current V S, Inputs = 8V 3.5 mA VS, Inputs = 8V 4 mA VS, Inputs = 8V, post radiation 4 mA IIL_18 Input Current Low V S = 18V, Inputs = 0V -5 0.08 5 µA VS = 18V, Inputs = 0V -10 10 µA VS = 18V, Inputs = 0V, post radiation -10 10 µA IIH_18 Input Current High V S, Inputs = 18V -5 0.08 5 µA VS, Inputs = 18V -10 10 µA VS, Inputs = 18V, post radiation -10 10 µA IIL_8 Input Current Low V S = 8V, Inputs = 0V -5 0.08 5 µA VS = 8V, Inputs = 0V -10 10 µA VS = 8V, Inputs = 0V, post radiation -10 10 µA IIH_8 Input Current High V S, Inputs = 8V -5 0.08 5 µA VS, Inputs = 8V -10 10 µA VS, Inputs = 8V, post radiation -10 10 µA VOH Output Voltage High VS = 8V, IOUT = 5mA V S - 0.75 V S - 0.45 V VS - 0.9 V

HS-4424DRH, HS4424DEH 5 FN8747.2 October 15, 2015 Submit Document Feedback VOL Output Voltage Low VS = 8V, IOUT = 5mA 0.45 0.8 V 0.8 V VOH Output Voltage High VS = 8V, IOUT = 50mA V S - 0.95 V S - 0.75 V VS - 1.1 V VOL Output Voltage Low VS = 8V, IOUT = 50mA 0.75 0.95 V 1.1 V VOH Output Voltage High VS = 12V, IOUT = 5mA V S - 0.75 V S - 0.45 V VS - 0.75 V VOL Output Voltage Low VS = 12V, IOUT = 5mA 0.45 0.8 V 0.8 V VOH Output Voltage High VS = 12V, IOUT = 50mA V S - 0.95 V S - 0.75 V VS - 1.1 V VOL Output Voltage Low VS = 12V, IOUT = 50mA 0.75 0.95 V 1.1 V VOH Output Voltage High VS = 18V, IOUT = 5mA V S - 0.75 V S - 0.45 V VS - 0.75 V VOL Output Voltage Low VS = 18V, IOUT = 5mA 0.45 0.8 V 0.8 V VOH Output Voltage High VS = 18V, IOUT = 50mA V S - 0.95 V S - 0.75 V VS - 1.1 V VOL Output Voltage Low VS = 18V, IOUT = 50mA 0.75 0.95 V 1.1 V VIH_18 Input Voltage High Threshold V S = 18V 3 V 3.1 V VIL_18 Input Voltage Low Threshold V S = 18V 0.8 V 0.8 V VIHYS_18 Input Voltage Threshold Hysteresis V S = 18V 100 mV VIH_12 Input Voltage High Threshold V S = 12V 3 V 3.1 V VIL_12 Input Voltage Low Threshold V S = 12V 0.8 V 0.8 V VHYS_12 Input Voltage Threshold Hysteresis V S = 12V 100 mV VIH_8 Input Voltage High Threshold V S = 8V 3 V 3.1 V VIL_8 Input Voltage Low Threshold V S = 8V 0.8 V 0.8 V VHYS_8 Input Voltage Threshold Hysteresis V S = 8V 100 mV UVLO_r Rising Undervoltage Lockout 7.2 7.5 7.8 V 6.9 7.95 V UVLO_f Falling Undervoltage Lockout 7.1 7.45 7.75 V 6.8 7.9 V HYS_UVLO Undervoltage Lockout Hysteresis UVLO_r - UVLO_f 23 mV 24 mV Min_PW Minimum Input Pulse Width 100 ns Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 5)T Y P MAX (Note 5)U N I T

HS-4424DRH, HS4424DEH 6 FN8747.2 October 15, 2015 Submit Document Feedback TRANSIENT RESPONSE tr, tf, Rise Time 10% to 90% of V OUT VS = 18V, CL = 4300pF 75 ns VS = 18V, CL = 4300pF 95 ns VS = 18V, CL = 4300pF, post radiation 95 ns Fall Time 90% to 10% of VOUT VS = 18V, CL = 4300pF 75 ns VS = 18V, CL = 4300pF 95 ns VS = 18V, CL = 4300pF, post radiation 95 ns Rise Time 10% to 90% of VOUT VS = 12V, CL = 4300pF 75 ns VS = 12V, CL = 4300pF 95 ns VS = 12V, CL = 4300pF, post radiation 95 ns Fall Time 90% to 10% of VOUT VS = 12V, CL = 4300pF 75 ns VS = 12V, CL = 4300pF 95 ns VS = 12V, CL = 4300pF, post radiation 95 ns Rise Time 10% to 90% of VOUT VS = 8V, CL = 4300pF 75 ns VS = 8V, CL = 4300pF 95 ns VS = 8V, CL = 4300pF, post radiation 95 ns Fall Time 90% to 10% of VOUT VS = 8V, CL = 4300pF 75 ns VS = 8V, CL = 4300pF 95 ns VS = 8V, CL = 4300pF, post radiation 95 ns tPHL, tPLH, 50% of Rising Input to 10% of Rising Output V S = 18V, CL = 4300pF 200 ns VS = 18V, CL = 4300pF 300 ns VS = 18V, CL = 4300pF, post radiation 300 ns 50% of Falling Input to 90% of Falling Output V S = 18V, CL = 4300pF 200 ns VS = 18V, CL = 4300pF 300 ns VS = 18V, CL = 4300pF, post radiation 300 ns 50% of Rising Input to 10% of Rising Output V S = 12V, CL = 4300pF 250 ns VS = 12V, CL = 4300pF 350 ns VS = 12V, CL = 4300pF, post radiation 350 ns 50% of Falling Input to 90% of Falling Output V S = 12V, CL = 4300pF 250 ns VS = 12V, CL = 4300pF 350 ns VS = 12V, CL = 4300pF, post radiation 350 ns 50% of Rising Input to 10% of Rising Output V S = 8V, CL = 4300pF 300 ns VS = 8V, CL = 4300pF 400 ns VS = 8V, CL = 4300pF, post radiation 400 ns 50% of Falling Input to 90% of Falling Output V S = 8V, CL = 4300pF 300 ns VS = 8V, CL = 4300pF 400 ns VS = 8V, CL = 4300pF, post radiation 400 ns NOTE: 5. Compliance to datasheet limits is assured by one or more methods; production test, characterization and/or design. Electrical Specifications VCC = 8V, 12V, 18V, TA= +25°C, unless otherwise noted. Boldface limits apply across the operating temperature range, -55°C to +125°C; over radiation total ionizing dose. (Continued) PARAMETER DESCRIPTION TEST CONDITIONS MIN (Note 5)T Y P MAX (Note 5)U N I T

HS-4424DRH, HS4424DEH 12 FN8747.2 October 15, 2015 Submit Document Feedback Applications Information Functional Description The HS-4424DxH MOSFET drivers are designed for easy implementation with a PWM controller, such as the HS-1825ARH, as the input control signal driver. The HS-4424DxH consist of two independent drivers sharing bias voltage and ground connections at the die level. Undervoltage Lockout and Operating Voltage Range The HS-4424DxH have a guaranteed UVLO of <8V across the operating temperature range. All devices are recommended to operate up to and are characterized and tested at a bias of 18V. The UVLO feature ensures that the internal MOSFET drivers have sufficient gate drive to operate in their saturated mode. When in a UVLO condition the HS-4424DxH outputs are put into a high impedance tri-stated mode. Characterization and testing occurs (as appropriate) at 8V, 12V and 18V and across the -55°C to +125°C operating temperature range. Input Characteristics The HS-4424DxH inputs are designed to be used with low voltage level signals (<1V for a low input level and >3V for a high input level) and also be capable of accepting input voltages up to the VCC level. Output Buffer The HS-4424DxH output buffers are designed to drive >2A of peak output current into high capacitance loads and can be paralleled to increase the output current capability. The output buffer uses a final drive stage comprised of a PNP lower and NPN upper complimentary pair of transistors for the high output current drive. To enhance the pull-up and pull-down of this bipolar pair, they are each paralleled with MOS devices to do so. Power Dissipation and Junction Temperature It is possible to exceed the +150°C maximum recommended junction temperature under certain load and power supply conditions. Calculate power dissipation using Equation 1; Where Pd = Power dissipation V = Supply voltage I = Operating supply current C = Load capacitance f = Operating frequency Calculate junction temperature T J using Equation 2: Where TJ = Junction temperature Pd = Power dissipation Theta JC = Junction-to-case thermal resistance T C = Case temperature PCB Layout Guidelines Use a ground plane in the PCB design, connect GND A and GND B pins directly to the ground plane in the same area, preferably close to the IC. Reference all input circuitry including IN A and IN B to a common node and reference all output circuitry including all OUT A and OUT B pins to a common node. Bypass each VCC pin to the ground plane with a 0.047µF ceramic chip capacitor in parallel with a 4.7µF low ESR solid tantalum capacitor. Clamp both OUT pins to VCC, each with a single diode. The 1n5819 (1A, 40V) Schottky diode is recommended. Pd V I 2 C V2 f+= (EQ. 1) TJ Pd Theta JC T C+= (EQ. 2)

HS-4424DRH, HS4424DEH 13 FN8747.2 October 15, 2015 Submit Document Feedback Die Characteristics Die Dimensions 4890µm x 3370µm (193mils x 133mils) Thickness: 483µm ±25.4µm (19mils ±1mil) Interface Materials GLASSIVATION Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ±1.0kÅ TOP METALLIZATION Type: AlSiCu Thickness: 16.0kÅ ±2kÅ BACKSIDE FINISH Silicon PROCESS Radiation Hardened Silicon Gate (DI) Assembly Related Information SUBSTRATE POTENTIAL Floating (DI) LID POTENTIAL Floating Additional Information WORST CASE CURRENT DENSITY < 2 x 105 A/cm2 TRANSISTOR COUNT 125 Weight of Packaged Device 0. 591 grams (typical) Lid Characteristics Finish: Gold Case isolation to any lead: 20 x10 9Ω (minimum) Metallization Mask Layout GND (5) IN B (7) OUT B (10) OUT B (11) VCC (12) VCC (13) GND (4) IN A (2) OUT A (15) OUT A (14)

HS-4424DRH, HS4424DEH Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN8747.2 October 15, 2015 For additional products, see www.intersil.com/en/products.html Submit Document Feedback About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support.

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE October 15, 2015 FN8747.2 Added part number HS-4424DEH throughout datasheet. July 1, 2015 FN8747.1 Abs Max ratings on page 4 - removed abs max input current and related text on page 13. ESD Ratings - changed Machine Model from: 1kV to: 200V and Charged Device Model from: 4kV to: 750V Changed over temp limits for UVLO Rising from: MIN/MAX 7.0/7.9 to: 6.9/7.95 and Falling MIN/MAX from: Changed over temp 8V, 5mA VOH limit MIN from V S - 0.75 to VS - 0.9. June 8, 2015 FN8747.0 Initial Release

HS-4424DRH, HS4424DEH 15 FN8747.2 October 15, 2015 Submit Document Feedback Package Outline Drawing K16.A

16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

Rev 2, 1/10 SIDE VIEW TOP VIEW SECTION A-A -D- -C- SEATING AND BASE PLANE -H- BASE LEAD FINISH METAL PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 BSC) 0.440 (11.18) 0.005 (0.13) MIN MAX 0.115 (2.92) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN 0.13 (3.30) MIN 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 LEAD FINISH adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. shall be molded to the bottom of the package to cover the leads. meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. NOTES: Dimensioning and tolerancing per ANSI Y14.5M - 1982. Controlling dimension: INCH. Index area: A notch or a pin one identification mark shall be located If a pin one identification mark is used in addition to a tab, the limits Measure dimension at all four corners. For bottom-brazed lead packages, no organic or polymeric materials Dimension shall be measured at the point of exit (beyond the