HD404318 RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 68

Technical content

Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 To all our customers

Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.

Rev. 6.0 Sept. 1998

Description

The HD404318 Series is 4-bit HMCS400-series microcomputer with large-capacity memory designed to increase program productivity. Each microcomputer has an A/D converter and input capture timer built in. They also come with high-voltage I/O pins that can directly drive a fluorescent display. The HD404318 Series includes four chips: the HD404318 with 8-kword ROM; the HD404316 with 6- kword ROM; the HD404314 with 4-kword ROM; the HD4074318 with 8-kword PROM. The HD4074318 is a PROM version ZTATä microcomputer. Programs can be written to the PROM by a PROM writer, which can dramatically shorten system development periods and smooth the process from debugging to mass production. (The PROM program specifications are the same as for the 27256.) ZTAT ä : Zero Turn Around Time ZTAT is a trademark of Hitachi Ltd.

Features

  • 34 I/O pins ¾ One input-only pin ¾ 33 input/output pins: 21 pins are high-voltage pins (40 V, max.)
  • On-chip A/D converter (8-bit · 8-channel)
  • Three timers ¾ One event counter input ¾ One timer output ¾ One input capture timer
  • 8-bit clock-synchronous serial interface (1 channel)
  • Alarm output
  • Built-in oscillators ¾ Ceramic or crystal oscillator ¾ External clock drive is also possible
  • Seven interrupt sources ¾ Two by external sources ¾ Three by timers ¾ One each by the A/D converter and serial interface
  • Two low-power dissipation modes ¾ Standby mode ¾ Stop mode
  • Instruction cycle time 1 ms (f osc = 4 MHz)

Ordering Information

Type Model Name ROM (words) RAM (digit) Package Mask ROM HD404314S 4,096 384 DP-42S HD404314H FP-44A HD404316S 6,144 DP-42S HD404316H FP-44A HD404318S 8,192 DP-42S HD404318H FP-44A ZTATä HD4074318S 8,192 DP-42S HD4074318H FP-44A Recommended PROM Programmers and Socket Adapters PROM Programmer Socket Adapter Manufacture Model Name Package Manufacturer Model Name DATA I/O Corp. 121B DP-42S Hitachi HS4318ESS01H FP-44A HS4318ESH01H AVAL Corp. PKW-1000 DP-42S Hitachi HS4318ESS01H FP-44A HS4318ESH01H

/SCK /SI /SO /TOC R4 1/AN5 AV CC VCC D 0/INT0 D 1/INT1 D 2/EVNB D 3/BUZZ D 4/STOPC NC R4 2/AN6 R4 3/AN7 R0 0/SCK R0 1/SI R0 2/SO R0 3/TOC TEST RESET OSC 1 OSC 2 AV SS R8 3 R8 2 R8 1 R8 0 D 8 D 7 D 6 D 5 D 4/STOPC D 3/BUZZ D 2/EVNB D 1/INT1 D 0/INT0 RA 1/Vdisp R2 3 R2 2 R2 1 R2 0 R1 3 R1 2 R1 1 R1 0 DP-42S V CC AV CC R3 0/AN0 R3 1/AN1 R3 2/AN2 R3 3/AN3 R4 0/AN4 R4 1/AN5 R4 2/AN6 R4 3/AN7 GND

Item Symbol DP-42S FP-44A I/O Function Power supply VCC 21 16 Applies power voltage GND 10 5 Connected to ground Vdisp (shared with RA1) 1 39 Used as a high-voltage output power supply pin when selected by the mask option Test TEST 6 1 I Cannot be used in user applications. Connect this pin to GND. Reset RESET 7 2 I Resets the MCU Oscillator OSC 1 8 3 I Input/output pin for the internal oscillator. Connect these pins to the ceramic or crystal oscillator, or OSC1 to an external oscillator circuit. OSC 2 94O Port D 0–D 8 22–30 17–21, 23–26 I/O Input/output pins addressed individually by bits; D0–D 8 are all high-voltage I/O pins. Each pin can be individually configured as selected by the mask option. RA 1 1 39 I One-bit high-voltage input port pin R0 0–R0 3, R3 0–R4 3 2–5, 12–19 40–43, 7–14 I/O Four-bit input/output pins consisting of standard voltage pins R1 0–R2 3, R8 0–R8 3 31–42 27–38 I/O Four-bit input/output pins consisting of high voltage pins Interrupt INT0, INT1 22, 23 17, 18 I Input pins for external interrupts Stop clear STOPC 26 21 I Input pin for transition from stop mode to active mode Serial interface SCK 2 40 I/O Serial interface clock input/output pin SI 3 41 I Serial interface receive data input pin SO 4 42 O Serial interface transmit data output pin Timer TOC 5 43 O Timer output pin EVNB 24 19 I Event count input pin Alarm BUZZ 25 20 O Square waveform output pin A/D converter AV CC 20 15 Power supply for the A/D converter. Connect this pin as close as possible to the V CC pin and at the same voltage as VCC . If the power supply voltage to be used for the A/D converter is not equal to VCC , connect a 0.1-mF bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.) AV SS 11 6 Ground for the A/D converter. Connect this pin as close as possible to GND at the same voltage as GND. AN 0–AN 7 12–19 7–14 I Analog input pins for the A/D converter

Pin Description in PROM Mode The HD4074318 is a PROM version of a ZTAT ä microcomputer. In PROM mode, the MCU stops operating, thus allowing the user to program the on-chip PROM. Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 13 9 R A 1/Vdisp I 24 0 R 00/SCK I/O V CC 34 1 R 01/SI I/O VCC 44 2 R 02/SO I/O 54 3 R 03/TOC I/O 6 1 TEST I VPP

72 RESET I RESET I

15 10 R3 3/AN3 I/O O 3 I/O 16 11 R4 0/AN4 I/O O 4 I/O 17 12 R4 1/AN5 I/O O 5 I/O 18 13 R4 2/AN6 I/O O 6 I/O 19 14 R4 3/AN7 I/O O 7 I/O 20 15 AV CC VCC 21 16 VCC VCC 22 17 D 0/INT0 I/O M 0 I 23 18 D 1/INT1 I/O M 1 I 24 19 D 2/EVNB I/O A1 I 25 20 D 3/BUZZ I/O A2 I 26 21 D 4/STOPC I/O 27 23 D 5 I/O A3 I 28 24 D 6 I/O A4 I 29 25 D 7 I/O A9 I 30 26 D 8 I/O VCC

Pin Number MCU Mode PROM Mode DP-42S FP-44A Pin I/O Pin I/O 31 27 R8 0 I/O CE I 32 28 R8 1 I/O OE I 33 29 R8 2 I/O A13 I 34 30 R8 3 I/O A14 I 35 31 R1 0 I/O A5 I 36 32 R1 1 I/O A6 I 37 33 R1 2 I/O A7 I 38 34 R1 3 I/O A8 I 39 35 R2 0 I/O A0 I 40 36 R2 1 I/O A10 I 41 37 R2 2 I/O A11 I 42 38 R2 3 I/O A12 I I/O: Input/output pin; I: Input pin; O: Output pin

(4,096× 10 bits) (6,144× 10 bits) (8,192× 10 bits) PC (14 bits) Instruction decoder SP (10 bits) B (4 bits) A (4 bits) ST (1 bit) CA (1 bit) ALU SPY (4 bits) Y (4 bits) SPX (4 bits) X (4 bits) W (2 bits) RAM (384× 4 bits) System controlInterrupt control Timer A Timer B Timer C Serial interface A/D converter Buzzer Internal data bus Internal data bus Internal address bus BUZZ AV CC AN 7 AV SS AN 0 SI SO SCK TOC EVNB INT0 INT1 Data bus High voltage pin Directional signal line GND VCC OSC 2 OSC 1 STOPC TEST RESET RA port

Vector Address Area ($0000–$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. Zero-Page Subroutine Area ($0000–$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000–$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000–$0FFF (HD404314), $0000–$17FF (HD404316), $0000–$1FFF (HD404318, HD4074318)): The entire ROM area can be used for program coding. $000F $0FFF $1000 $0010 $003F $0040 Vector address (16 words) Zero-page subroutine (64 words) Pattern (4,096 words) HD404314 Program (4,096 words) HD404316 Program (6,144 words) $0000 $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F JMPL instruction (jump toRESET,STOPC routine) JMPL instruction (jump toINT routine) JMPL instruction (jump to timer A routine) JMPL instruction (jump to timer B routine) JMPL instruction (jump to timer C routine) JMPL instruction (jump to A/D converter routine) JMPL instruction (jump toINT routine) JMPL instruction (jump to serial routine) HD404318, HD4074318 Program (8,192 words) $17FF $1800 $1FFF Note: Since the ROM address areas between $0000-$0FFF overlap, the user can determine how these areas are to be used. Figure 1 ROM Memory Map

A/D channel register (ACR) $000 $000 $040 $050 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $020 $023 $033 $034 $00A $00B $00E $00F W W R/W W W W W W W W W W R R R R W R/W R/W R/W R/W R/W $3C0 RAM-mapped registers Memory registers (MR) Stack (64 digits) Interrupt control bits area Port mode register A (PMRA) Serial mode register (SMR) Serial data register lower (SRL) Serial data register upper (SRU) Timer mode register A (TMA) Timer mode register B1 (TMB1) Timer B (TRBL/TWBL) (TRBU/TWBU) Miscellaneous register (MIS) Timer mode register C (TMC) Timer C (TRCL/TWCL) (TRCU/TWCU) Register flag area Port R0 DCR (DCR0) Port R3 DCR (DCR3) Not used 1. Two registers are mapped on the same area ($00A, $00B, $00E, $00F). 2. Undefined. Timer read register B lower (TRBL) Timer read register B upper (TRBU) Timer read register C lower (TRCL) Timer read register C upper (TRCU) Timer write register B lower (TWBL) Timer write register B upper (TWBU) Timer write register C lower (TWCL) Timer write register C upper (TWCU) R: Read only W: Write only R/W: Read/write $180 Notes: $016 RA/D data register lower (ADRL)$017 $024 $025 $026 $018 $019 $01A $3FF A/D data register upper (ADRU) A/D mode register 1 (AMR1) A/D mode register 2 (AMR2) R W W W Port mode register B (PMRB) Port mode register C (PMRC) Timer mode register B2 (TMB2) Not used Port R4 DCR (DCR4)W W W W $030 Data (304 digits) Not used Not used Not used Not used -000 0000 0000 Undefined Undefined -000 0000 *2/0000 00-- 0000 0000 0000 0000 1000 0000 --00 0000 00-0 -000 0000 Undefined *2/0000 Undefined Initial values after reset $03F Figure 2 RAM Memory Map and Initial Values

Table 1 Initial Values of Flags after MCU Reset Item Initial Value Interrupt flags/mask Interrupt enable flag (IE) 0 Interrupt request flag (IF) 0 Interrupt mask (IM) 1 Bit registers Watchdog timer on flag (WDON) 0 A/D start flag (ADSF) 0 Input capture status flag (ICSF) 0 Input capture error flag (ICEF) 0 IAD off flag (IAOF) 0 RAM enable flag (RAME) 0 Bit 3 Bit 2 Bit 1 Bit 0 IMTA (IM of timer A) IFTA (IF of timer A) IM1 (IM ofINT1) IF1 (IF ofINT1) IMTC (IM of timer C) IFTC (IF of timer C) IMTB (IM of timer B) IFTB (IF of timer B) IMS (IM of serial) IFS (IF of serial) IMAD (IM of A/D) IFAD (IF of A/D) $0000 $0001 $0002 $0003 Interrupt control bits area IM0 (IM ofINT0) IF0 (IF ofINT0) RSP (Reset SP bit) IE (Interrupt enable flag) ICSF (Input capture status flag) $020 $021 $022 $023 Register flag area ADSF (A/D start flag) WDON (Watchdog on flag) Not used ICEF (Input capture error flag) RAME (RAM enable flag)IF: Interrupt request flag IM: Interrupt mask IE: Interrupt enable flag SP: Stack pointer Bit 3 Bit 2 Bit 1 Bit 0 RAM Address IAOF (IAD off flag) Not used Not used Figure 3 Interrupt Control Bits and Register Flag Areas Configuration

(B) (A) (W) (X) (Y) (SPX) (SPY) (CA) (ST) (PC) (SP)11 11 Accumulator B register W register X register Y register SPX register SPY register Carry Status Program counter Initial value: 0, no R/W Stack pointer Initial value: $3FF, no R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: Undefined, R/W Initial value: 1, no R/W Figure 6 Registers and Flags

Register Indirect Addressing Mode: The contents of the W, X, and Y registers (10 bits total) are used as a RAM address. Direct Addressing Mode: A direct addressing instruction consists of two words. The first word contains the opcode, and the contents of the second word (10 bits) are used as a RAM address. Memory Register Addressing Mode (LAMR, XMRA): The memory registers (MR), which are located in 16 addresses from $040 to $04F, are accessed with the LAMR and XMRA instructions. 30 300 W X Y Opcode Register Indirect Addressing 2nd instruction word RAM address Direct Addressing Instruction 9 0 RAM address 1st instruction word Memory Register Addressing RAM address 000100 Opcode Instruction Figure 7 RAM Addressing Modes

Direct Addressing Mode: A program can branch to any address in ROM memory space by executing the JMPL, BRL, or CALL instruction. Current Page Addressing Mode: A program can branch to any address in the current page (256 words per page) by executing the BR instruction. Zero-Page Addressing Mode: A program can branch to any subroutine located in the zero-page subroutine area ($0000–$003F) by executing the CAL instruction. Table Data Addressing Mode: A program can branch to an address determined by the contents of 4-bit immediate data, the accumulator, and the B register by executing the TBR instruction. Direct Addressing 2nd instruction word Program counter Current Page Addressing Program counter 1st instruction word Zero-Page Addressing Operand Table Data Addressing 0 9 OperandOpcode 013 Operand Opcode Program counter 013 Operand Opcode BA 9Opcode 00000000Program counter 013 Figure 8 ROM Addressing Modes

Table 2 Instruction Set Classification Instruction Type Function Number of Instructions Immediate Transferring constants to the accumulator, B register, and RAM. 4 Register-to-register Transferring contents of the B, Y, SPX, SPY, or memory registers to the accumulator RAM addressing Available when accessing RAM in register indirect addressing mode 13 RAM register Transferring data between the accumulator and memory. 10 Arithmetic Performing arithmetic operations with the contents of the accumulator, B register, or memory. Compare Comparing contents of the accumulator or memory with a constant 12 RAM bit manipulation Bit set, bit reset, and bit test. 6 ROM addressing Branching and jump instructions based on the status condition. 8 Input/output Controlling the input/output of the R and D ports; ROM data reference with the P instruction Control Controlling the serial communication interface and low-power dissipation modes. Total: 101 instructions

$000,0 $000,2 $000,3 $001,0 $001,1 $001,2 $001,3 $002,0 $002,1 $002,2 $002,3 $003,0 $003,1 Interrupt request Priority Controller IFS IMS $003,2 $003,3 INT0 interrupt INT1 interrupt Timer A interrupt Timer B interrupt Timer C interrupt A/D interrupt Serial interrupt Priority OrderVector Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E (RESET,STOPC) Figure 9 Interrupt Control Circuit

execution* IE reset Interrupt acceptance Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Vector address generation Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a two-cycle instruction. Stacking Figure 10 Interrupt Processing Sequence

The MCU has three operating modes as shown in table 3. Transitions between operating modes are shown in figure 11. Table 3 Operations in Each Operating Mode Function Active Mode Standby Mode Stop Mode System oscillator OP OP Stopped CPU OP Retained Reset RAM OP Retained Retained Timer A OP OP Reset Timers B, C OP OP Reset Serial interface OP OP Reset A/D OP OP Reset I/O OP Retained Reset Note: OP implies in operation

MCU Operation Sequence: The MCU operates in the sequence shown in figure 13 and figure 14. The low-power mode operation sequence is shown in figure 14. With the IE flag cleared and an interrupt flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt flags are cleared or all interrupts are masked. Power ON Reset MCU RAME = 0 IE ← 0 Stack ← (PC), (CA), (ST) No Yes IF = 1? RESET = 0? SBY/STOP instruction IM = 0 IE = 1 RAME = 1Instruction execution Reset input PC ← vector address No No No Yes Yes MCU operation cycle PC ← (PC)+1Low-power mode operation cycle (figure 15) Figure 13 MCU Operating Sequence (Power ON)

IF = 1 and IM = 0? Hardware NOP execution ←PC Next Iocation MCU operation cycle Standby mode IF = 1 and IM = 0? Hardware NOP execution PC Next Iocation Instruction execution Stop mode No Yes No Yes STOPC = 0? RAME = 1 Reset MCU No Yes Figure 14 MCU Operating Sequence (Low-Power Mode Operation)

Table 4 Oscillator Circuit Examples Circuit Configuration Circuit Constants External clock operation External oscillator OSC Open OSC 2 Ceramic oscillator (OSC 1, OSC2) OSC C 1 OSC R fCeramic GND Ceramic oscillator: CSA4.00MG (Murata) R f = 1 MW –20% C 1 = C2 = 30 pF –20% Crystal oscillator (OSC 1, OSC2) OSC C 1 OSC R fCrystal GND L SC R S C O OSC 1 OSC 2 R f = 1 MW –20% C 1 = C2 = 10 to 22 pF –20% Crystal: Equivalent to circuit shown below C 0 = 7 pF max. R S = 100 W max. Notes: 1. Since the circuit constants change depending on the crystal or ceramic oscillator and stray capacitance of the board, the user should consult with the crystal or ceramic oscillator manufacturer to determine the circuit parameters. 2. Wiring among OSC1, OSC2, and elements should be as short as possible, and must not cross other wiring (see figure 16).

The MCU has 33 input/output pins (D0–D 8, R0–R4, R8) and one input-only pin (RA1). The following describes the features of the I/O ports.

  • The 21 pins consisting of D0–D 8, R1, R2, and R8 are all high-voltage I/O pins. RA1 is a high-voltage input-only pin. These high-voltage pins can be equipped with or without pull-down resistance, as selected by the mask option.
  • All standard output pins are CMOS output pins. However, the R02/SO pin can be programmed for NMOS open-drain output.
  • In stop mode, input/output pins go to the high-impedance state
  • All standard input/output pins have pull-up MOS built in, which can be individually turned on or off by software Table 5 Control of Standard I/O Pins by Program MIS3 (bit 3 of MIS) 0 1 DCR 0 1 0 1 P D R 01010101 CMOS buffer PMOS — — — On — — — On Note: — indicates off. Bit Initial value Read/Write Bit name W W W W DCR0, DCR3, DCR4 Data control register (DCR0: $030, DCR3: $033, DCR4: $034) Bits 0 to 3 CMOS Buffer Control CMOS buffer off (high impedance) CMOS buffer on Register DCR0 DCR3 DCR4 Bit 3 R0 3 R3 3 R4 3 Correspondence between ports and DCR bits Bit 2 R0 2 R3 2 R4 2 Bit 1 R0 1 R3 1 R4 1 Bit 0 R0 0 R3 0 R4 0 DCR03, DCR33, DCR43, DCR02, DCR32, DCR42, DCR01, DCR31, DCR41, DCR00, DCR30, DCR40 Figure 17 Data Control Register (DCR)

Table 6 Circuit Configurations of Standard I/O Pins I/O Pin Type Circuit Pins Input/output pins VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 PDR Input control signal DCR R0 0, R01, R03 R3 0–R3 3, R4 0–R4 3 VCC VCC Pull-up control signal Buffer control signal Output data Input data HLT MIS3 DCR PDR Input control signal MIS2 R0 2 Peripheral function pins Input/ output pins VCC VCC Pull-up control signal Output data Input data HLT MIS3 SCK SCK SCK Output pins VCC VCC Pull-up control signal PMOS control signal Output data HLT MIS3 SO MIS2 SO VCC VCC Pull-up control signal Output data HLT MIS3 TOC TOC Notes on next page.

AN 0–AN 7 Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes.

Table 7 Circuit Configurations for High-Voltage Input/Output Pins I/O Pin Type With Pull-Down Resistance Without Pull-Down Resistance Pins Input/output pins VCC Input data Input control signal HLT Output data Vdisp Pull-down resistance VCC Input data Input control signal Output data HLT D 0–D 8, R1 0–R1 3, R2 0–R2 3, R8 0–R8 3 Input pins Input data Input control signal RA 1 Peripheral function pins Output pins VCC HLT Output data Vdisp Pull-down resistance VCC HLT Output data BUZZ Input pins Input data Pull-down resistance Vdisp Input data INT0, INT1, EVNB, STOPC Notes: 1. In stop mode, the MCU is reset and the peripheral function selection is cancelled. The HLT signal goes low, and input/output pins the enter high-impedance state. 2. The HLT signal is 1 in active and standby modes. 3. The circuits of HD4074318 are without pull-down resistance.

Note: The on/off status of each transistor and the peripheral function mode of each pin can be set independently. W MIS3 W MIS2 Not used Not used MIS2 CMOS Buffer On/Off Selection for Pin R0 2/SO Miscellaneous register (MIS: $00C) CMOS on CMOS off MIS3 Pull-Up MOS On/Off Selection Pull-up MOS off Pull-up MOS on (refer to table 5) Figure 20 Miscellaneous Register (MIS)

The MCU has a built-in prescaler labeled as prescaler S (PSS), which divides the system clock and then outputs divided clock signals to the peripheral function modules, as shown in figure21. Timer A Timer B Timer C Serial System clock Prescaler SClock selector Figure 21 Prescaler Output Supply

The MCU has three built-in timers: A, B, and C. The functions of each timer are listed in table 7. Timer A Timer A is an 8-bit free-running timer that has the following features:

  • One of eight internal clocks can be selected from prescaler S according to the setting of timer mode register A (TMA: $008)
  • An interrupt request can be generated when timer counter A (TCA) overflows
  • Input clock frequency must not be modified during timer A operation Table 7 Timer Functions Functions Timer A Timer B Timer C Clock source Prescaler S Available Available Available External event — Available — Timer functions Free-running Available Available Available Event counter — Available — Reload — Available Available Watchdog — — Available Input capture — Available — Timer output PWM — — Available

Timer B is an 8-bit multifunction timer that includes free-running, reload, and input capture timer features. These are described as follows.

  • By setting timer mode register B1 (TMB1: $009), one of seven internal clocks supplied from prescaler S can be selected, or timer B can be used as an external event counter
  • By setting timer mode register B2 (TMB2: $026), detection edge type of EVNB can be selected
  • By setting timer write register BL, BU (TWBL, BU: $00A, $00B), timer counter B (TCB) can be written to during reload timer operation
  • By setting timer read register BL, BU (TRBL, BU: $00A, $00B), the contents of timer counter B can be read out
  • Timer B can be used as an input capture timer to count the clock cycles between trigger edges input as an external event
  • An interrupt can be requested when timer counter B overflows or when a trigger input edge is received during input capture operation

(TCB) Timer mode register B2 (TMB2) EVNB Selector System clock øPER Prescaler S (PSS) Edge detector Edge detection control signal Timer write register B lower (TWBL) Timer mode register B1 (TMB1) Timer write register B upper (TWBU) Clock Free-running timer control signal Timer read register B lower (TRBL) Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Overflow Internal data bus 128 512 2048 Figure 24 Timer B Free-Running and Reload Operation Block Diagram

(TCB) Internal data bus Timer mode register B2 (TMB2) EVNB Selector System clock øPER Prescaler S (PSS) Edge detector Edge detection control signal Timer mode register B1 (TMB1) Clock Input capture timer control signal Timer read register B lower (TRBL) Interrupt request flag of timer B (IFTB) Timer read register BU (TRBU) Overflow Read signal Input capture status flag (ICSF) Input capture error flag (ICEF) Error controller 128 512 2048 Figure 25 Timer B Input Capture Operation Block Diagram

Timer C is an 8-bit multifunction timer that includes free-running, reload, and watchdog timer features, which are described as follows.

  • By setting timer mode register C (TMC: $00D), one of eight internal clocks supplied from prescaler S can be selected
  • By selecting pin TOC with bit 2 (PMRA2) of port mode register A (PMRA: $004), timer C output (PWM output) is enabled
  • By setting timer write register CL, CU (TWCL, CU: $00E, $00F), timer counter C (TCC) can be written to
  • By setting timer read register CL, CU (TRCL, CU: $00E, $00F), the contents of timer counter C can be read out
  • An interrupt can be requested when timer counter C overflows
  • Timer counter C can be used as a watchdog timer for detecting runaway program

(TCC) Port mode register A (PMRA) Selector System clock øPER Prescaler S (PSS) Timer write register C lower (TWCL) Timer mode register C (TMC) Timer write register C upper (TWCU) Clock Free-running timer control signal Timer read register C lower (TRCL) Interrupt request flag of timer C (IFTC) Timer read register CU (TRCU) Overflow TOC Timer output control signal Timer output control logic Watchdog timer controller Watchdog on flag (WDON) System reset signal Internal data bus 128 512 1024 2048 Figure 28 Timer C Block Diagram

$FF + 1 $00 Timer C count value Overflow Time CPU operation Normal operation Timer C clear Normal operation Timer C clear Program runaway Normal operationReset Figure 31 Watchdog Timer Operation Flowchart Notes on Use When using the timer output as PWM output, note the following point. From the update of the timer write register until the occurrence of the overflow interrupt, the PWM output differs from the period and duty settings, as shown in table 8. The PWM output should therefore not be used until after the overflow interrupt following the update of the timer write register. After the overflow, the PWM output will have the set period and duty cycle. Table 8 PWM Output Following Update of Timer Write Register PWM Output Mode Timer Write Register is Updated during High PWM Output Timer Write Register is Updated during Low PWM Output Free running Timer write register updated to value N Interrupt request Timer write register updated to value N Interrupt request T × (N' + 1) Reload Timer write register updated to value N Interrupt request TT × (255 – N)T Timer write register updated to value N Interrupt request TT × (255 – N) T

The MCU has an alarm output function built in. By setting port mode register C (PMRC: $025), one of four alarm frequencies supplied from the PSS can be selected. Table 9 Port Mode Register C PMRC Bit 3 Bit 2 System Clock Divisor 00 ‚ 2048 1 ‚ 1024 10 ‚ 512 1 ‚ 256 Internal data bus 256 512 1024 2048 Selector System clock øPER Prescaler S (PSS) Alarm output control signal BUZZ Alarm output controller Port mode register C (PMRC) Port mode register A (PMRA) Figure 32 Alarm Output Function Block Diagram

The MCU has a one-channel serial interface built in with the following features.

  • One of 13 different internal clocks or an external clock can be selected as the transmit clock. The internal clocks include the six prescaler outputs divided by two and by four, and the system clock.
  • During idle states, the serial output pin can be controlled to be high or low output
  • Transmit clock errors can be detected
  • An interrupt request can be generated after transfer has completed when an error occurs Table 10 Serial Interface Operating Modes SMR PMRA Bit 3 Bit 1 Bit 0 Operating Mode 1 0 0 Continuous clock output mode

1 Transmit mode

1 Transmit/receive mode

(PMRC) SCK Selector System clock øPER Prescaler S (PSS) Idle controller Serial mode register (SMR) Clock Serial data register (SR) Serial interrupt request flag (IFS) Selector 1/2 1/2 SI SO Octal counter (OC) I/O controller Transfer control signal 128 512 2048 Figure 33 Serial Interface Block Diagram

/,/#01/#06 /#13/#19/#1E/#1F State MCU reset PMRA write SMR write PMRC write SCK pin STS wait state Transmit clock wait state Transfer state Transmit clock wait state STS wait state Port selection External clock selection Output level control in idle states Dummy write for state transition Output level control in idle states Data write for transmission Undefined LSB MSB Flag reset at transfer completionExternal clock mode State MCU reset PMRA write SMR write PMRC write STS wait state Transfer state Transmit clock wait state STS wait state Port selection Internal clock selection Output level control in idle states Data write for transmission Output level control in idle states Undefined LSB MSB Flag reset at transfer completionInternal clock mode (input) instruction write SRL, SRU STS SO pin IFS SCK pin (output) instruction write SRL, SRU STS SO pin IFS Figure 36 Example of Serial Interface Operation Sequence

Transmit clock erors are detected as illustrated in figure 37. Transfer completion (IFS 1) Interrupts inhibited IFS 0 SMR write IFS = 1 Transmit clock error processing Normal termination Yes No Transmit clock error detection flowchart /#0A/#0B/#10/#11 Transmit clock error detection procedure State SCK pin (input) Transmit clock wait state Transfer state Transfer state Transmit clock wait state Noise Transfer state has been entered by the transmit clock error. When SMR is written, IFS is set. Flag set because octal counter reaches 000. Flag reset at transfer completion. SMR write IFS 12 345678 Figure 37 Transmit Clock Error Detection

Table 11 Transmit Clock Selection PMRC SMR Bit 0 Bit 2 Bit 1 Bit 0 System Clock Divisor Transmit Clock Frequency 0000 ‚ 2048 4096t cyc 1 ‚ 512 1024tcyc 10 ‚ 128 256t cyc 1 ‚ 32 64tcyc 100 ‚ 8 16tcyc 1 ‚ 24 tcyc 1000 ‚ 4096 8192t cyc 1 ‚ 1024 2048tcyc 10 ‚ 256 512t cyc 1 ‚ 64 128tcyc 100 ‚ 16 32tcyc 1 ‚ 48 tcyc Bit Initial value Read/Write Bit name W SMR3 W SMR2 W SMR0 W SMR1 Serial mode register (SMR: $005) SMR2 SMR0SMR1SMR3 R0 0/SCK Mode Selection R0 0 SCK SCK Output Input Clock Source Prescaler External clock Prescaler Division Ratio Refer to table 11 Output System clock Figure 38 Serial Mode Register (SMR)

W PMRC3 W PMRC2 W PMRC0 Undefined W PMRC1 Port mode register C (PMRC: $025) PMRC1 Output Level Control in Idle States Low level High level PMRC0 Serial Clock Division Ratio Prescaler output divided by 2 Prescaler output divided by 4 Alarm output function. Refer to table 9. Figure 39 Port Mode Register C (PMRC)

The MCU also contains a built-in A/D converter that uses a sequential comparison method with a resistance ladder. It can perform digital conversion of eight analog inputs with 8-bit resolution. The following describes the A/D converter.

  • A/D mode register 1 (AMR1: $019) is used to select digital or analog ports
  • A/D mode register 2 (AMR2: $01A) is used to set the A/D conversion speed and to select digital or analog ports
  • The A/D channel register (ACR: $016) is used to select an analog input channel
  • A/D conversion is started by setting the A/D start flag (ADSF: $020, 2) to 1. After the conversion is completed, converted data is stored in the A/D data register, and at the same time, the A/D start flag is cleared to 0
  • By setting the I AD off flag (IAOF: $021, 2) to 1, the current flowing through the resistance ladder can be cut off even while operating in standby or active mode IAD off flag (IAOF) Selector A/D channel register (ACR) A/D mode register 2 (AMR2) A/D mode register 1 (AMR1) A/D interrupt request flag (IFAD) Encoder A/D data register (ADRU, L) A/D start flag (ADSF) D/A AV CC AV SS Operating mode signal (1 in stop mode) Internal data bus+ Comp A/D controller AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Control signal for conversion time Figure 40 A/D Converter Block Diagram
  • Use the SEM or SEMD instruction for writing to the A/D start flag (ADSF)
  • Do not write to the A/D start flag during A/D conversion
  • Data in the A/D data register during A/D conversion is undefined
  • Since the operation of the A/D converter is based on the clock from the system oscillator, the A/D converter does not operate in stop mode. In addition, to save power while in stop mode, all current flowing through the converter’s resistance ladder is cut off.
  • If the power supply for the A/D converter is to be different from V CC , connect a 0.1-mF bypass capacitor between the AVCC and AVSS pins. (However, this is not necessary when the AVCC pin is directly connected to the VCC pin.)
  • The port data register (PDR) is initialized to 1 by an MCU reset. At this time, if pull-up MOS is selected as active by bit 3 of the miscellaneous register (MIS3), the port will be pulled up to V CC . When using a shared R port/analog input pin as an input pin, clear PDR to 0. Otherwise, if pull-up MOS is selected by MIS3 and PDR is set to 1, a pin selected by bit 1 of the A/D mode register as an analog pin will remain pulled up. Bit Initial value Read/Write Bit name W AMR13 W AMR12 W AMR10 W AMR11 AMR10

1 AN 0

A/D mode register 1 (AMR1: $019) AMR11 AN 1 AMR12 2/AN2 Mode Selection R3 2 AN 2 AMR13 R3 3/AN3 Mode Selection R3 3 AN 3 R3 0/AN0 Mode Selection R3 0 R3 1/AN1 Mode Selection R3 1 Figure 41 A/D Mode Register 1 (AMR1)

Assemble all parts including the HD404318 Series on a board, noting the points described below. 1. Connect layered ceramic type capacitors (about 0.1 mF) between AVCC and AVSS , between VCC and GND, and between used analog pins and AVSS . 2. Connect unused analog pins to AVSS . AV AN AN to AN AV CC SS AV AN AN AN to AN AV CC SS AV AN AN AN to AN AV CC SS 1. When not using an A/D converter. V GND CC V GND CC V GND CC 2. When using pins AN and AN but not using AN to AN .01 2 7 3. When using all analog pins. 0.1 µF 3× 0.1 µF 9× 0.1 µF Figure 49 Example of Connections (1)

Between the VCC and GND lines, connect capacitors designed for use in ordinary power supply circuits. An example connection is described in figure 50. No resistors can be inserted in series in the power supply circuit, so the capacitors should be connected in parallel. The capacitors are a large capacitance C1 and a small capacitance C2. V GND CC V GND CC C1 C2 Figure 50 Example of Connections (2)

Item Symbol Value Unit Notes Supply voltage VCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +14.0 V 1 Pin voltage VT –0.3 to VCC + 0.3 V 2 VCC – 45 to VCC + 0.3 Total permissible input currentå IO 70 mA 4 Total permissible output current –åIO 150 mA 5 Maximum input current IO 4 mA 6, 7 20 mA 6, 8 Maximum output current –I O 4 mA 9, 10 30 mA 10, 11 Operating temperature Topr –20 to +75 °C Storage temperature Tstg –55 to +125 °C Notes: Permanent damage may occur if these absolute maximum ratings are exceeded. Normal operation must be under the conditions stated in the electrical characteristics tables. If these conditions are exceeded, the LSI may malfunction or its reliability may be affected. 1. Applies to pin TEST (VPP ) of HD4074318. 2. Applies to all standard voltage pins. 3. Applies to high-voltage pins. 4. The total permissible input current is the total of input currents simultaneously flowing in from all the I/O pins to GND. 5. The total permissible output current is the total of output currents simultaneously flowing out from V CC to all I/O pins. 6. The maximum input current is the maximum current flowing from each I/O pin to GND. 7. Applies to ports R3 and R4. 8. Applies to port R0. 9. Applies to ports R0, R3, and R4. 10. The maximum output current is the maximum current flowing from V CC to each I/O pin. 11. Applies to ports D0–D 8, R1, R2, and R8.

Electrical Characteristics

DC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Notes Input high voltage VIH RESET, SCK, SI, INT0, INT1, STOPC, EVNB 0.8VCC —V CC + 0.3 V OSC 1 VCC – 0.5 — V CC + 0.3 V Input low voltage VIL RESET, SCK, SI –0.3 — 0.2V CC V INT0, INT1, STOPC, EVNB VCC – 40 — 0.2V CC V OSC 1 –0.3 — 0.5 V Output high voltage V OH SCK, SO, TOC VCC – 0.5 — — V –I OH = 0.5 mA Output low voltage V OL SCK, SO, TOC — — 0.4 V I OL = 0.4 mA I/O leakage current IL| RESET, SCK, SI, SO, TOC, OSC 1 —— 1 mAV in = 0 V to VCC 1 INT0, INT1, STOPC, EVNB —— 2 0 mAV in = VCC – 40 to VCC 1 Current dissipation in active mode I CC VCC — — 5.0 mA V CC = 5 V, fOSC = 4 MHz 2, 5 — — 8.0 mA 2, 6 Current dissipation in standby mode I SBY VCC — — 2.0 mA V CC = 5 V, fOSC = 4 MHz Current dissipation in stop mode I STOP VCC —— 1 0 mAV CC = 5 V 4, 5 —— 2 0 mA 4, 6 Stop mode retaining voltage V STOP VCC 2— — V Notes: 1. Excludes current flowing through pull-up MOS and output buffers. 2. ICC is the source current when no I/O current is flowing while the MCU is in reset state. Test conditions: MCU: Reset Pins: RESET, TEST at GND R0, R3, R4 at VCC D 0–D 8, R1, R2, R8, RA1 at Vdisp

  1. ISBY is the source current when no I/O current is flowing while the MCU timer is operating. Test conditions: MCU: I/O reset Standby mode Pins: RESET at VCC TEST at GND R0, R3, R4 at VCC D 0–D 8, R1, R2, R8, RA1 at Vdisp 4. This is the source current when no I/O current is flowing. Test conditions: Pins: R0, R3, R4 at V CC D 0–D 8, R1, R2, R8, RA1 at GND 5. Applies to the HD404314, HD404316 and HD404318. 6. Applies to the HD4074318. I/O Characteristics for Standard Pins (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH R0, R3, R4 0.7V CC —V CC + 0.3 V Input low voltage VIL R0, R3, R4 –0.3 — 0.3V CC V Output high voltage V OH R0, R3, R4 V CC – 0.5 — — V –I OH = 0.5 mA Output low voltage V OL R3, R4 — — 0.4 V I OL = 1.6 mA R0 — — 2.0 V I OL = 10 mA Input leakage current IL| R0, R3, R4 — — 1 mAV in = 0 V to VCC 1 Pull-up MOS –I PU R0, R3, R4 30 150 300 mAV CC = 5 V, Vin = 0 V 2 30 80 180 mA3 Notes: 1. Output buffer current is excluded. 2. Applies to the HD404314, HD404316, and HD404318. 3. Applies to the HD4074318.

I/O Characteristics for High-Voltage Pins (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , T a = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Input high voltage VIH D 0–D 8, R1, R2, R8, RA1 0.7VCC —V CC + 0.3 V Input low voltage V IL D 0–D 8, R1, R2, R8, RA1 VCC – 40 — 0.3V CC V Output high voltage V OH D 0–D 8, R1, R2, R8, BUZZ VCC – 3.0 — — V –I OH = 15 mA VCC – 2.0 — — V –I OH = 10 mA VCC – 1.0 — — V –I OH = 4 mA Output low voltage V OL D 0–D 8, R1, R2, R8, BUZZ —— V CC – 37 V V disp = VCC – 40 V 1 —— V CC – 37 V 150 k W at VCC – 40 V 2 I/O leakage current IL|D 0–D 8, R1, R2, R8, RA1, BUZZ —— 2 0 mAV in = VCC – 40 V to VCC 3 Pull-down MOS current I PD D 0–D 8, R1, R2, R8, BUZZ 200 600 1000 mAV disp = VCC – 35 V, Vin = VCC Notes: 1. Applies to pins with pull-down MOS as selected by the mask option . 2. Applies to pins without pull-down MOS as selected by the mask option. 3. Excludes output buffer current. A/D Converter Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , Ta = –20 to +75°C, unless otherwise specified) Item Symbol Pins Min Typ Max Unit Test Condition Note Analog supply voltage AVCC AV CC VCC – 0.3 VCC VCC + 0.3 V 1 Analog input voltage AVin AN 0–AN 7 AV SS —A V CC V Current flowing between AVCC and AVSS IAD — — 200 mAV CC = AVCC = 5.0 V Analog input capacitance CA in AN 0–AN 7 — — 30 pF Resolution 8 8 8 Bit Number of input channels 0 — 8 Chan nel Absolute accuracy — — –2.0 LSB Conversion time 34 — 67 t cyc Input impedance AN 0–AN 7 1— — M W Note: 1. Connect this to VCC if the A/D converter is not used.

AC Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , Ta = –20 to +75°C) Item Symbol Pins Min Typ Max Unit Test Condition Note Clock oscillation frequency fOSC OSC 1, OSC2 0.4 4 4.5 MHz System clock divided by 4 Instruction cycle time tcyc 0.89 1 10 ms Oscillation stabilization time (ceramic oscillator) t RC OSC 1, OSC2 — — 7.5 ms 1 Oscillation stabilization time (crystal oscillator) t RC OSC 1, OSC2 — — 40 ms 1 External clock high width tCPH OSC 1 9 2——n s 2 External clock low width tCPL OSC 1 9 2——n s 2 External clock rise time tCPr OSC 1 — — 20 ns 2 External clock fall time tCPf OSC 1 — — 20 ns 2 INT0, INT1, EVNB high widths tIH INT0, INT1, EVNB 2 ——t cyc 3 INT0, INT1, EVNB low widths tIL INT0, INT1, EVNB 2 ——t cyc 3 RESET low width t RSTL RESET 2 ——t cyc 4 STOPC low width t STPL STOPC 1 ——t RC 5 RESET rise time t RSTr RESET — — 20 ms 4 STOPC rise time t STPr STOPC — — 20 ms 5 Input capacitance C in All input pins except TEST — — 30 pF f = 1 MHz, V in = 0 V TEST — — 30 pF 6 — — 180 pF 7 Notes: 1. The oscillation stabilization time is the period required for the oscillator to stabilize in the following situations: a. After VCC reaches 4.0 V at power-on. b. After RESET input goes low when stop mode is cancelled. c. After STOPC input goes low when stop mode is cancelled. To ensure the oscillation stabilization time at power-on or when stop mode is cancelled, RESET or STOPC must be input for at least a duration of tRC . When using a crystal or ceramic oscillator, consult with the manufacturer to determine what stabilization time is required, since it will depend on the circuit constants and stray capacitance. 2. Refer to figure 51. 3. Refer to figure 52. 4. Refer to figure 53. 5. Refer to figure 54. 6. Applies to the HD404314, HD404316, and HD404318. 7. Applies to the HD4074318.

Serial Interface Timing Characteristics (VCC = 4.0 to 5.5 V, GND = 0 V, Vdisp = VCC – 40 V to VCC , Ta = –20 to +75°C, unless otherwise specified) During Transmit Clock Output Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1— — t cyc Load shown in figure 56 1 Transmit clock high width tSCKH SCK 0.4 — — t Scyc Load shown in figure 56 1 Transmit clock low width tSCKL SCK 0.4 — — t Scyc Load shown in figure 56 1 Transmit clock rise time tSCKr SCK — — 80 ns Load shown in figure 56 1 Transmit clock fall time tSCKf SCK — — 80 ns Load shown in figure 56 1 Serial output data delay time tDSO SO — — 300 ns Load shown in figure 56 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time tHSI SI 200 — — ns 1 During Transmit Clock Input Item Symbol Pins Min Typ Max Unit Test Condition Note Transmit clock cycle time tScyc SCK 1— — t cyc 1 Transmit clock high width tSCKH SCK 0.4 — — t Scyc 1 Transmit clock low width tSCKL SCK 0.4 — — t Scyc 1 Transmit clock rise time tSCKr SCK — — 80 ns 1 Transmit clock fall time tSCKf SCK — — 80 ns 1 Serial output data delay time t DSO SO — — 300 ns Load shown in figure 56 1 Serial input data setup time t SSI SI 100 — — ns 1 Serial input data hold time tHSI SI 200 — — ns 1 Note: 1. Refer to figure 55. tCPr tCPf VCC – 0.5 V 0.5 V OSC 1 tCPH tCPL 1/fCP Figure 51 External Clock Timing

Please pay attention to the following items regarding ROM out. On ROM out, fill the ROM area indicated below with 1s to create the same data size for the HD404314 and HD404316 as an 8-kword version (HD404318). An 8-kword data size is required to change ROM data to mask manufacturing data since the program used is for an 8-kword version. This limitation applies when using an EPROM or a data base. Vector address Zero-page subroutine (64 words) Pattern & program (4,096 words) Not used Vector address Zero-page subroutine (64 words) Pattern & program (6,144 words) Not used ROM 4-kword version: HD404314 Address $1000–$1FFF ROM 6-kword version: HD404316 Address $1800–$1FFF $0000 $000F $0010 $003F $0040 $0FFF $1000 $1FFF $0000 $000F $0010 $003F $0040 $17FF $1800 $1FFF Fill this area with 1s

HD404314/HD404316/HD404318 Option List Please check off the appropriate applications and enter the necessary information. 4. ROM Code Media EPROM: Ceramic oscillator Crystal oscillator External clock f = MHz f = MHz f = MHz 5. System Oscillator for OSC1 and OSC2 RA1 without pull-down resistance Vdisp 3. RA1/Vdisp Note: If even only one pin is selected with I/O option E, pin RA1/Vdisp must be selected to function as Vdisp. The upper bits and lower bits are mixed together. The upper five bits and lower five bits EPROM: The upper bits and lower bits are separated. The upper five bits and lower five bits are programmed to different EPROMS. DP-42S FP-44A 7. Package Please specify the first type below (the upper bits and lower bits are mixed together), when using the EPROM on-package microcomputer type (including ZTAT™ version). Used Not used 6. Stop mode Date of order Customer Department Name ROM code name LSI number HD404314 HD404316 HD404318 1. ROM Size 4-kword 6-kword 8-kword D0/INT0 D1/INT1 D2/EVNB D3/BUZZ D4/STOPC Pin name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O option DE 2. I/O Options D: Without pull-down resistance RA R10 R11 R12 R13 R20 R21 R22 R23 R80 R81 R82 R83 RA1 Pin name I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O option DE Selected in option (3) E: With pull-down resistance

  1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi’s sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail- safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor products. Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.