HS4-3282-8

HS-3282 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• ARlNC Specification 429 Compatible
• Data Rates of 100 Kilobits or 12.5 Kilobits
• Separate Receiver and Transmitter Section
• Dual and Independent Receivers, Connecting Directly to ARINC Bus
• Serial to Parallel Receiver Data Conversion
• Parallel to Serial Transmitter Data Conversion
• Word Lengths of 25 or 32 Bits
• Parity Status of Received Data
• Generate Parity of Transmitter Data
• Automatic Word Gap Timer
• Single 5V Supply
• Low Power Dissipation
• Full Military Temperature Range

Description

The HS-3282 is a high performance CMOS bus interface circuit that is intended to meet the requirements of ARINC Specification 429, and similar encoded, time multiplexed serial data protocols. This device is intended to be used with the HS-3182, a monolithic Dl bipolar differential line driver designed to meet the specifications of ARINC 429. The ARINC 429 bus interface circuit consists of two (2) receivers and a transmitter operating independently as shown in Figure 1. The two receivers operate at a frequency that is ten up to eight (8) ARINC data words for transmission serially. will cause odd parity to be used in the output data stream.

Ordering Information

PACKAGE TEMP. RANGE PART NUMBER PKG. NO. CERDIP -55 oC to +125oC HS1-3282-8 F40.6 SMD# 5962-8688001QA F40.6 CLCC -40 oC to +85oC HS4-3282-9+ J44.A -55oC to +125oC HS4-3282-8 J44.A SMD# 5962-8688001XA J44.A File Number 2964.2CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

HS-3282 (CERDIP) TOP VIEW HS-3282 (CLCC) TOP VIEW VDD 429DI1(A) 429DI1(B) 429DI2(A) 429DI2(B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 NC MR TX CLK CLK NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND 46 3 BD15 BD12 NC D/R1 BD14 EN2 BD11 NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD01 BD00 NC 429DI2(B) TXCLK CLK 429DI2(A) NC NC BD10 BD09 BD08 BD07 BD06 BD04 BD03 GND BD02 BD05 429DI1(A) SEL EN1 4041424344 2827262524232221201918 VDD BD13 D/R2 429DI1(B) MR NC HS-3282

PIN SYMBOL SECTION DESCRIPTION 1V CC Recs/Trans Supply pin 5 volts±5%. 2 429 DI1 (A) Receiver ARlNC 429 data input to Receiver 1. 3 429 DI1 (B) Receiver ARlNC 429 data input to Receiver 1. 4 429 Dl2 (A) Receiver ARINC 429 data input to Receiver 2. 5 429 DI2 (B) Receiver ARINC 429 data input to Receiver 2. D/R1 Receiver Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched. 7 D/R2 Receiver Device ready flag output from Receiver 2 indicating a valid data word is ready to be fetched. 8 SEL Receiver Bus Data Selector - Input signal to select one of two 16-bit words from either Receiver 1 or 2. EN1 Receiver Input signal to enable data from Receiver 1 onto the data bus. 10 EN2 Receiver Input signal to enable data from Receiver 2 onto the data bus. 11 BD15 Recs/Trans Bi-directional data bus for fetching data from either of the Receivers, or for loading data into the Transmitter memory or control word register. See Control Word Table for description of Control Word bits. 12 BD14 Recs/Trans See Pin 11. 13 BD13 Recs/Trans See Pin 11. 14 BD12 Recs/Trans See Pin 11. 15 BD11 Recs/Trans See Pin 11. 16 BD10 Recs/Trans See Pin 11. 17 BD09 Recs/Trans See Pin 11. 18 BD08 Recs/Trans See Pin 11. 19 BD07 Recs/Trans See Pin 11. 20 BD06 Recs/Trans See Pin 11. 21 GND Recs/Trans Circuit Ground. 22 BD05 Recs/Trans See Pin 11. 23 BD04 Recs/Trans See Pin 11. Control Word function not applicable. 24 BD03 Recs/Trans See Pin 11. Control Word function not applicable. 25 BD02 Recs/Trans See Pin 11. Control Word function not applicable. 26 BD01 Recs/Trans See Pin 11. Control Word function not applicable. 27 BD00 Recs/Trans See Pin 11. Control Word function not applicable. PL1 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory. 29 PL2 Transmitter Parallel load input signal loading the first 16-bit word into the Transmitter memory and initiates data transfer into the memory stack. 30 TX/R Transmitter Transmitter flag output to indicate the memory is empty. HS-3282

31 429D0 Transmitter Data output from Transmitter 32 429D0 Transmitter Data output from Transmitter. 33 ENTX Transmitter Transmitter Enable input signal to initiate data transmission from FIFO memory. CWSTR Recs/Trans Control word input strobe signal to latch the control word from the databus into the control word register. 35 - - No connection. Must be left open. 36 - - No connection. Must be left open or tied low but never tied high. 37 CLK Recs/Trans External clock input. May be either ten (10) or eighty (80) times the data rate. If using both ARINC data rates it must be ten (10) times the highest data rate, (typically 1MHz). 38 TXCLK Transmitter Transmitter Clock output. Delivers a clock frequency equal to the transmitter data rate. MR Recs/Trans Master Reset. Active low pulse used to reset FIFO, bit counters, gap timer, word count signal, TX/R and various other flags and controls. Master reset does not reset the control word register. Usually only used on Power-Up or System Reset. 40 - - No Connection. Pin Description (Continued) PIN SYMBOL SECTION DESCRIPTION 28 40 393837363534333231302927262524232221 13 1 2345678910111214151617181920 NCNC NC HS-3282

timing and parity functions on a single, low power LSl circuit. been incorporated into the bus interface circuit. that is 10 times the data rate. remains active. (Logic “0” on SLFTST Enables Self Test). BD06 SDENB1 Signal to Activate the Source/Destination (S/D) Decoder for Receiver 1. (Logic “1” activates S/D Decoder). accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. be accepted by the Receiver 1. If SDENB1 = “0” this bit becomes a don’t care. BD09 SDENB2 Signal to activate the Source/Destination (S/D) Decoder for Receiver 2. (Logic “1” activates S/D Decoder). accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. be accepted by the Receiver 2. If SDENB2 = “0” this bit becomes a don’t care. divided by ten (10). If TXSEL = “1” then transmitter data rate is equal to the clock rate divided by eighty (80). TABLE 1. ARINC 429 32-BIT DATA FORMAT

11 LSB

28 MSB

29 Sign

32 Parity Status

13 LSB 11

8 Parity Status 32

ignore the partially received data word. No Source/Destination (S/D) in 25-Bit format.

• The Line Receiver functions as a voltage level translator. It transforms the 10 volt differential line voltage, ARINC 429 format, into 5 volt internal logic level.
• The output of the Line Receiver is one of two inputs to the Self-Test Data Selector (SEL). The other input to the Data Selector is the Self-Test Signal from the Transmitter section.
• The incoming data, either Self-Test or ARlNC 429, is double sampled by theWord Gap Timer to generate a Data Clock. The Receiver sample frequency (RCVCLK), 1MHz, or 125kHz, is generated by the Receiver/Transmit- ter Timing Circuit. This sampling frequency is ten times the Data Rate to ensure no data ambiguity.
• The derived data clock then shifts the data down a 32-Bit long Data Shift Register (Data S/RI). The Data Word Length is selectable for either 25 Bits or 32 Bits long by the Control Signal (WLSEL). As soon as the data word is completely received, an internal signal (WDCNT1) is gen- erated by the Word Gap Timer Circuit.
• The Source/Destination (S/D) Decoder compares the user set code (X and Y) with Bits 9 and 10 of the Data Word. If the two codes are matched, a positive signal is generated to enable the WDCNT1 signal to latch in the received data. Otherwise, the data word is ignored and no latching action takes place. The S/D Decoder can be Enabled and Disabled by the control signal S/D ENB. If the data word is latched, an indicator flag ( D/R1) is set. This indicates a valid data word is ready to be fetched by the user.
• After the receiver data has been shifted down the shift register, it is placed in a holding register. The device ready flag will then be set indicating that data is ready to be fetched. If the data is ignored and left in the holding regis- ter, it will be written over when the next data word is received.
• The received data in the 32-bit holding register is placed on the bus in the form of two (2)16-bit words regardless of whether the format is for 32 or 25-bit data words. Either word can be accessed first or repeatedly until the next received data word falls into the holding register.
• The parity of the incoming word is checked and the status (i.e., logic “0” for odd parity and logic “1” for even parity) stored in the receiver latch and output on BD08 during the Word No. 1.
• Assuming the user desires to access the data, he first sets the Data Select Line (SEL) to a Logic “0” level and pulses the Enable ( EN1) line. This action causes the Data Selector (SELl) to select the first-data word, which con- tains the label field and Enable it onto the Data Bus. To obtain the second data word, the user sets the SEL line to a Logic “1” level and pulse the Enable ( EN1) line again. The Enable pulse duration is matched to the user circuit requirement needed to read the Data Word from the Data Bus. The second Enable pulse is also used to reset the Device Ready ( D/R1) flip-flop. This completes a receiving cycle. TABLE 2B. WORD 2 FORMAT BI-DIRECTIONAL BlT# FUNCTION ARINC BIT#

15 Sign 29

14 MSB 28

TABLE 3. ARINC 25-BIT DATA FORMAT

9 LSB

24 MSB

25 Parity Status

8 Parity Status 25

15 MSB 24

0 LSB 9

FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM

16 SEL 1

Absolute Maximum Ratings Thermal Information Input, Output or I/O Voltage Applied Operating Conditions Operating Temperature Range oC to +70oC Thermal Resistance θJA (oC/W) θJC (oC/W) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX ARlNC INPUTS Pins 2-3,4-5 Logic “1” Input Voltage V lH VDD = 5.25V 6.7 13.0 V Logic “0” Input Voltage V IL VDD = 5.25V -13.0 -6.7 V Null Input Voltage V NUL VDD = 4.75V, 5.25V -2.5 +2.5 V Common Mode Voltage V CH VDD = 4.75V, 5.25V -5.0 +5.0 V Input Leakage I lH VDD = 5.25V, VIN =±6.5V - 200 µA Input Leakage I lL VDD = 5.25V, VIN = 0.0V -450 - µA Differential Input Impedance RI V DD = 5.25V, VIN = +5V, -5V 12 - k Ω Input lmpedance to VDD RH V DD = 5.25V, VlN = 0V 12 - k Ω Input lmpedance to GND RG V DD = Open, VlN = 5.0V 12 - k Ω BIDIRECTIONAL INPUTS Pins 11-20, 22-27 Logic “1” Input Voltage V IH VDD = 5.25V 2.1 - V Logic “0” Input Voltage V IL VDD = 4.75V - 0.7 V Input Leakage l IH VDD = 5.25V,VIN = 5.25V - 1.5 µA Input Leakage I lL VDD = 5.25V, VIN = 0.0V -1.5 - µA ALL OTHER INPUTS Pins 8-10, 28, 29, 33, 34, 37, 39 Logic “1” Input Voltage V IH VDD = 5.25V 3.5 - V Logic “0” Input Voltage V IL VDD = 4.75V - 0.7 V Input Leakage I lH VDD = 5.25V, VIN = 5.25V - 10 µA Input Leakage I lL VDD = 5.25V, VIN = 0.0V -75 - µA OUTPUTS Pins 6, 7, 11-20, 22-27, 30-32, 38, Supply Pin 1 Logic “1” Output Voltage V OH VDD = 4.75V, IOH = -1.5mA 2.7 - V Logic “0” Output Voltage V OL VDD = 4.75V lOL = 1.8mA - 0.4 V Standby Supply Current l CC1 VDD = 5.25V, VIN = 0V Except 9,10, 29 = 5.25V -2 0 m A Operating Supply Current l CC2 VDD = 5.25V, VIN = 5.25V Except 8, 33 = 0.0V, CLK = 1MHz -2 0 m A HS-3282

TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX Clock Frequency FC V DD = 4.75V, 5.25V - 1 MHz Data Rate 1/ FD V DD = 4.75V, 5.25V - 100 kHz Data Rate 2/ FD V DD = 4.75V, 5.25V - 12.5 kHz Master Reset Pulse Width TMR V DD = 4.75V, 5.25V 200 - ns RECEIVER TIMING Receiver Ready Time From 32nd Bit 1/ TD/R2 V DD = 4.75V, 5.25V - 16 µs Receiver Ready Time From 32nd Bit 2/ TD/R2 V DD = 4.75V, 5.25V - 128 µs Device Ready to Enable Time TD/REN V DD = 4.75V, 5.25V 0 - ns Data Enable Pulse Width TEN V DD = 4.75V, 5.25V 200 - ns Data Enable to Data Enable Time TENEN V DD = 4.75V, 5.25V 50 - ns Data Enable to Device Ready Reset Time TEND/R V DD = 4.75V, 5.25V - 200 ns Output Data Valid to Enable Time TENDATA V DD = 4.75V, 5.25V - 200 ns Data Enable to Data Select Time TENSEL V DD = 4.75V, 5.25V 20 - ns Data Select to Data Enable Time TSELEN V DD = 4.75V, 5.25V 20 - ns Output Data Disable Time TDATAEN V DD = 4.75V, 5.25V - 80 ns CONTROL WORD TIMING Control Word Strobe Pulse Width TCWSTR V DD = 4.75V, 5.25V 130 - ns Control Word Setup Time TCWSET V DD = 4.75V, 5.25V 130 - ns Control Word Hold Time TCWHLD V DD = 4.75V, 5.25V 0 - ns TRANSMITTER FIFO Write Timing Parallel Load Pulse Width TPL V DD = 4.75V, 5.25V 200 - ns Parallel Load to Parallel Load 2 Delay TPL12 V DD = 4.75V, 5.25V 0 - ns Transmitter Ready Delay Time TTX/R V DD = 4.75V, 5.25V - 840 ns Data Word Setup Time TDWSET V DD = 4.75V, 5.25V 110 - ns Data Word Hold Time TDWHLD V DD = 4.75V, 5.25V 0 - ns TRANSMITTER Output Timing Enable Transmit to Output Data Valid Time 1/ TENDAT V DD = 4.75V, 5.25V - 25 µs Enable Transmit to Output Data Valid Time 2/ TENDAT V DD = 4.75V, 5.25V - 200 µs Output Data Bit Time 1/ TBlT V DD = 4.75V, 5.25V 4.95 5.05 µs Output Data Bit Time 2/ TBlT V DD = 4.75V, 5.25V 39.6 40.4 µs Output Data Null Time 1/ TNULL V DD = 4.75V, 5.25V 4.95 5.05 µs Output Data Null Time 2/ TNULL V DD = 4.75V, 5.25V 39.6 40.4 µs HS-3282

Data Word Gap Time 1/ TGAP V DD = 4.75V, 5.25V 39.6 40.4 µs Data Word Gap Time 2/ TGAP V DD = 4.75V, 5.25V 316.8 323.2 µs Data Transmission Word to TX/R Set Time TDTX/R V DD = 4.75V, 5.25V - 400 ns Enable Transmit Turnoff Time TENTX/R V DD = 4.75V, 5.25V 0 - ns REPEATER OPERATION TIMING Data Enable to Parallel Load Delay Time TENPL V DD = 4.75V, 5.25V 0 - ns Data Enable Hold for Parallel Load Time TPLEN V DD = 4.75V, 5.25V 0 - ns Enable Transmit Delay Time TTX/REN V DD = 4.75V, 5.25V 0 - ns NOTES: 1. 100kHz Data Rate. 2. 12.5kHz Data Rate. Electrical Performance SpecificationsVDD = 5V±5%, TA = 0oC to +70oC (HS-3282-5), TA = -55oC to +125oC (HS-3282-8) PARAMETER SYMBOL (NOTE 1) CONDITIONS LIMITS UNITSMIN MAX Differential Input Capacitance CD V DD = Open, f = 1MHz, Note 2, 3 - 20 pF Input Capacitance to VDD CH V DD = GND, f = 1MHz, Note 2, 3 - 20 pF lnput Capacitance to GND CG V DD = Open, f = 1MHz, Note 2, 3 - 20 pF Input Capacitance Cl V DD = Open, f = 1MHz, Note 2, 4 - 15 pF Output Capacitance CO V DD = Open, f = 1MHz, Note 2, 5 - 15 pF Clock Rise Time TLHC CLK = 1MHz, From 0.7V to 3.5V - 10 ns Clock Fall Time THLC CLK = 1MHz, From 3.5V to 0.7V - 10 ns Input Rise Time TLHI From 0.7V to 3.5V, Note 6 - 15 ns Input Fall Time THLI From 3.5V to 0.7V, Note 6 - 15 ns NOTES: 1. The parameters listed in this table are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes affecting these parameters. 2. All measurements are referenced to device GND. 3. Pins 2-3, 4-5. 4. Pins 8-10, 28, 29, 33, 34, 37, 39. 6. Pins 8-20, 22-29, 33, 34. TA = -55oC to +125oC (HS-3282-8) (Continued) PARAMETER SYMBOL CONDITIONS LIMITS UNITSMIN MAX HS-3282

NOTES: 1. Resistors = 47kΩ , 5%, 1/4W (Min) 2. GND = Ground 3. V DD = +5.5V,±0.5V 4. C = 0.01mF/Socket (Min) 5. F0 = 100kHz, F1 = F0/2, . . . F15 = F14/2 VDD DI1(A) DI1(B) DI2(A) DI2(B) D/R1 D/R2 SEL EN1 EN2 BD15 BD14 BD13 BD12 BD11 BD10 BD09 BD08 BD07 BD06 NC MR TX CLK CLK NC NC CWSTR ENTX 429D0 429D0 TX/R PL2 PL1 BD00 BD01 BD02 BD03 BD04 BD05 GND F10 F11 F12 F13 F14 F15 VDD NC NC GND GND GND NC NC NC NC GND VDD NC NC NC F15 VDDC 46 3 BD15 BD12 NC D/R1 BD14 EN2 BD11 NC NC CWSTR ENTX TX/R PL2 PL1 BD01 BD00 NC DI2(B) TXCLK CLK DI2(A) NC NC BD10 BD09 BD08 BD07 BD06 BD04 BD03 GND BD02 BD05 DI1(A) SEL EN1 4041424344 2827262524232221201918 VCC BD13 D/R2 DI1(B) MR NC NC NC NC VDD F15 F14 F13 F12 F11 NC NC V DD GND NC NC NC VDD GND NC F15 NC NC GND GND NCNC F10 F09 F08 F07 F06 GND F05 F04 F03 F02 C HS-3282

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 246 x 224 x 19 mils) (6250 x 5700 x 483µm) METALLIZATION: Type: Si-Al Thickness: 11k Å ±2kÅ GLASSIVATION: Type: SiO2 Thickness: 8kA±1kÅ WORST CASE CURRENT DENSITY: 2 x 105 A/cm2 Metallization Mask Layout HS-3282 (6)D/R1 (2) 429DI1(A) (40) N/C (36) N/C (4) 429DI2(A) (5) 429DI2(B) BD09 (17) BD15 (11) SEL (8) D/R2 (7) (3) 429DI1(B) (1) VDD (39)MR (37) CLK (38) TX CLK EN1 (9) EN1 (10) BD14 (12) BD13 (13) BD12 (14) BD11 (15) BD10 (16) BD08 (18) BD07 (19) BD06 (20) GND (21) BD05 (22) BD04 (23) BD03 (24) BD02 (25) BD01 (26) (34)CWSTR (33) ENTX (32)429D0 (31) 429D0 (35) N/C (30) TX/R (29)PL2 (28)PL1 (27) BD00 HS-3282