HS-3530ARH_12 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Radiation Performance *Product capability established by initial characterization. The EH version is acceptance tested on a wafer by wafer basis to 50krad(Si) at low dose rate.
- Wide Range AC Programming
- Wide Range DC Programming
- Dielectrically Isolated Device Islands
- Short Circuit Protection
- Full -55°C to +125°C Military Temperature Range Pin Configurations HS2-3530ARH (CAN), MACY1-X8 TOP VIEW HS9-3530ARH, HS9-3530AEH(FLATPACK), CDFP3-F10 TOP VIEW
Ordering Information
TEMP. RANGE (°C) 5962F9568701QGA HS2-3530ARH-8 -55 to +125 5962F9568701VGA HS2-3530ARH-Q -55 to +125 5962F9568702VGA HS2-3530AEH-Q -55 to +125 5962F9568701VXC HS9-3530ARH-Q -55 to +125 5962F9568702VXC HS9-3530AEH-Q -55 to +125 5962F9568701V9A HS0-3530ARH-Q -55 to +125 5962F9568702V9A HS0-3530AEH-Q -55 to +125 HS2-3530ARH/PROTO HS2-3530ARH/Proto -55 to +125 HS9-3530ARH/PROTO HS9-3530ARH/Proto -55 to +125 ISET OUTPUTINVERTING OFFSET NON-INVERTING OFFSET NULLINPUT INPUT NULL 1NC OFFSET - IN + IN V - ISET V + OUTPUT OFFSET NC December 12, 2012 FN4653.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1999, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
HS-3530ARH, HS-3530AEH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4653.1 December 12, 2012 For additional products, see www.intersil.com/product_tree Die Characteristics DIE DIMENSIONS: 1720µm x 1390µm x 533µm ±25.4µm (68 mils x 55 mils x 21 mils ±1 mil) INTERFACE MATERIALS GLASSIVATION Type: Silox (SiO 2) Thickness: 8.0kA ±1.0kA TOP METALLIZATION Type: AlSiCu Thickness: 16.0kA ±2kA SUBSTRATE: Radiation Hardened Silicon Gate, Dielectric Isolation BACKSIDE FINISH: Silicon ASSEMBLY RELATED INFORMATION SUBSTRATE POTENTIAL: Unbiased (DI) ADDITIONAL INFORMATION WORST CASE CURRENT DENSITY: <2.0 x 105 A/cm2 TRANSISTOR COUNT: Metallization Mask Layout Pin Numbers shown are for the Can Package HS-3530ARH, HS-3530AEH OFFSET (1) ISET (8) NC V+ (7)NCOUTPUT (6) OFFSET (5) NC V- (4) NC IN+ (3) IN- (2)