HS-2420RH_03 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

 Electrically Screened to SMD # 5962-95669  QML Qualified per MIL-PRF-38535 Requirements  Maximum Acquisition Time (Maximum Over Temperature)  TTL Compatible Control Input  No Latch-Up

Applications

 Data Acquisition Systems  D to A Deglitcher  Auto Zero Systems  Peak Detector G a t e d O p A m p Functional Diagram IN- IN+ OFFSET ADJUST OFFSET ADJUST NC OUTPUT SAMPLE /HOLD GND NC HOLD CAPACITOR NC NC CONTROL

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962R9566901VCC HS1B-2420RH-Q -55 to 125 OFFSET ADJUST OUTPUT HOLD CAPACITOR - INPUT + INPUT SAMPLE / HOLD CONTROL V-GND HS-2420RH 34 5 513 Data Sheet February 2003

Offset and Gain Adjustment Offset Adjustment The offset voltage of the HS-2420RH may be adjusted using a 100kΩ trim pot, as shown in Figure 15. The recommended adjustment procedure is: 1. Apply 0V to the sample-and-hold input, and a square wave to the S/H control. 2. Adjust the trim pot for 0V output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. The two circuits shown below demonstrate how to adjust gain error at the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input voltage that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. 5. Measure the output hold voltage (V-10 NOMINAL). Adjust the trim pot for an output hold voltage of: V-10 NOMINAL() 10V–()+

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Die Characteristics DIE DIMENSIONS: 97 mils x 61 mils x 19 mils METALLIZATION: Type: Al Thickness: 16kÅ ± 2kÅ GLASSIVATION: Type: Silox Thickness: 14kÅ ± 2kÅ WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 TRANSISTOR COUNT: PROCESS: Bipolar-Di Metallization Mask Layout HS-2420RH HS-2420RH