HS-2420EH RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 11

Technical content

Features

  • Electrically screened to SMD # 5962-95669
  • QML qualified per MIL-PRF-38535 requirements
  • Maximum acquisition time (maximum over-temperature)
  • TTL compatible control input
  • Radiation tolerance * Only the EH device is wafer-by-wafer acceptance tested at the low dose rate and guaranteed to 50krad(Si). The 100krad(Si) limit is established by characterization only.
  • N o l a t c h - u p

Applications

  • Data acquisition systems
  • D to A deglitcher
  • Auto zero systems
  • P e a k d e t e c t o r
  • Gated op amp OFFSET ADJUST OUTPUT HOLD CAPACITOR - INPUT + INPUT SAMPLE/ HOLD CONTROL V-GND 34 5 513 HS-2420EH

FIGURE 1. FUNCTIONAL DIAGRAM

FN8727 Rev 0.00 Page 2 of 11 March 17, 2015 HS-2420EH

14 LD METAL-SEALED SIDE-BRAZED CERAMIC DIP

MIL-STD-1835, CDIP2-T14 TOP VIEW IN- IN+ OFFSET ADJUST OFFSET ADJUST NC OUTPUT SAMPLE /HOLD GND NC HOLD CAPACITOR NC NC CONTROL Pin Descriptions PIN # PIN NAME DESCRIPTION

1 IN- Inverting input to the operational amplifier

2 IN+ Non-inverting input to the operational amplifier

3, 4 OFFSET ADJUST Connect a 100k Ω potentiometer across these pins to null out the offset voltage.

5 V- Negative power supply

6, 8, 10, 12 NC No connect pin.

7 OUTPUT Output of the unity gain amplifier

9 V+ Positive Power Supply

11 HOLD CAPACITOR Connect the hold capacitor between this pin and GND.

13 GND Ground connection of the device

14 SAMPLE/HOLD CONTROL Control inpu t to the series analog switch.

Ordering Information

(Note 1) PART NUMBER (Note 2) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962R9566902VCC HS1B-2420EH-Q -55 to +125 14 Ld SBDIP D14.3 HS1B-2420EH/PROTO HS1B-2420EH/PROTO -55 to +125 14 Ld SBDIP D14.3 NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table must be used when ordering.

FN8727 Rev 0.00 Page 8 of 11 March 17, 2015 Offset and Gain Adjustment Offset Adjustment The offset voltage of the HS-2420EH may be adjusted using a 100kΩ trim pot, as shown in Figure 17. The recommended adjustment procedure is: 1. Apply 0V to the sample-and-hold input, and a square wave to the S/H control. 2. Adjust the trim pot for 0V output in the hold mode. Gain Adjustment The linear variation in pedestal voltage with sample-and-hold input voltage causes a -0.06% gain error (CH = 1000pF). In some applications (D/A deglitcher, A/D converter) the gain error can be adjusted elsewhere in the system, while in other applications it must be adjusted at the sample-and-hold. Figures 18 and 19 illustrate how to implement gain error adjust on the sample-and-hold. The recommended procedure for adjusting gain error is: 1. Perform offset adjustment. 2. Apply the nominal input volt age that should produce a +10V output. 3. Adjust the trim pot for +10V output in the hold mode. 4. Apply the nominal input voltage that should produce a -10V output. Measure the output hold voltage (V-10 NOMINAL). Adjust the trim pot for an output hold voltage of:

FN8727 Rev 0.00 Page 9 of 11 March 17, 2015 Die Characteristics DIE DIMENSIONS: 97mils x 61mils x 19mils METALLIZATION: Type: Al Thickness: 16kÅ  2kÅ GLASSIVATION: Type: Silox Thickness: 14kÅ  2kÅ WORST CASE CURRENT DENSITY: 2.0 x 105A/cm2 TRANSISTOR COUNT: PROCESS: Bipolar-Di Metallization Mask Layout HS-2420EH

FN8727 Rev 0.00 Page 10 of 11 March 17, 2015 HS-2420EH Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE March 17, 2015 FN8727.0 Initial Release

FN8727 Rev 0.00 Page 11 of 11 March 17, 2015 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be mea- sured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a par- tial lead paddle. For this configuration dimension b3 replaces di- mension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)

14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A- 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D- 0.785 - 19.94 - E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 -6 S2 0.005 - 0.13 -7  90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M- 0.0015 - 0.038 2 N1 4 1 4 8 Rev. 0 4/94