HS-0548RH INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 6
Technical content
Features
- Electrically Screened to SMD # 5962-95694
- QML Qualified per MIL-PRF-38535 Requirements 4RAD(Si)
- No Latch-Up
- No Channel Interaction During Overvoltage
- Guaranteed r ON Matching
- Break-Before-Make Switching
Applications
- Data Acquisition Systems
- Control Systems
- Telemetry Pinouts HS-0548RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW HS-0549RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW
Ordering Information
MKT. NUMBER TEMP. RANGE (oC) 5962D9569401VEA HS1-0548RH-Q -55 to 125 5962D9569401VEC HS1B-0548RH-Q -55 to 125 5962D9569402VEA HS1-0549RH-Q -55 to 125 5962D9569402VEC HS1B-0549RH-Q -55 to 125 AO ENABLE -VSUPPLY IN 1 IN 2 IN 3 OUT IN 4 GND SUPPLY IN 5 IN 6 IN 7 IN 8 ENABLE -VSUPPLY IN 1A IN 2A IN 3A OUTA IN 4A SUPPLY IN 1B IN 2B IN 3B IN 4B OUT B GND Data Sheet August 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999
FIGURE 1. ACCESS TIME
FIGURE 5. ADDRESS DECODER FIGURE 6. MULTIPLEX SWITCH F0 = 100kHz 50% duty cycle; VIL = 0.8V Max; VIH = 4.0V Min.
DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 = +15.5V,±.0.5V V3 = -15.5V,±0.5V R 1 = 10k Ω ,±5% C 1 = 0.01µF minimum (per socket) D 1 = 1N4002 or equivalent (per board) 50% duty cycle, VIL = 0.8V Max; VIH = 4.0V Min HS-0549RH STATIC BURN-IN TEST CIRCUIT V1 = +5.5V,±0.5V V2 = +15.5V,±0.5V V3 = -15.5V,±0.5V R 1 = 10k Ω , ±10% C 1 = 0.01µF minimum (per socket) D 1 = 1N4002 or equivalent (per board) Burn-In/Life Test Circuits (Continued) V2V3 D 1 C 1 R 1 R 1 D 1 C 1 V2V3 D 1 C 1 R 1 R 1 D 1 C 1 Irradiation Circuits HS-0549RH R 1 = R2 = 10kΩ ±5% HS-0548RH R 1 = 10kΩ ±5% +5V -15V +1V R 1 R 2 +1V +15V 14 +5V -15V +1V R 1 +1V +15V HS-0548RH, HS-0549RH
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: 83 mils x 108 mils x 19 mils INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kÅ ±0.7kÅ Top Metallization: Type: Al Thickness: 16kÅ ±2kÅ Substrate: CMOS, DI ASSEMBLY RELATED INFORMATION: Substrate Potential: Floating ADDITIONAL INFORMATION: Worst Case Current Density: 1.4 x 105 A/cm2 Transistor Count: 253 Metallization Mask Layout HS-0548RH HS-0549RH NOTE: Pad Numbers Correspond to DIP Pin Numbers Only IN 6 IN 7 IN 8 OUT IN 4 IN 3 IN 5 GND IN 2 IN 1 A2 A1 A0 EN IN3B IN4B OUT B OUT A IN4A IN3A IN2A IN1A IN2B IN1B GND A1 A0 EN HS-0548RH, HS-0549RH