HS-0508RH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically Screened to SMD # 5962-95692
  • QML Qualified per MIL-PRF-38535 Requirements 4RAD(Si)
  • No Latch-Up
  • No Channel Interaction During Overvoltage
  • 44V Maximum Power Supply
  • Break-Before-Make Switch

Applications

  • Data Acquisition Systems
  • Control Systems
  • Telemetry Pinouts HS-0508RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW HS-0509RH GDIP1-T16 (CERDIP) OR CDIP2-T16 (SBDIP) TOP VIEW

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962D9569201VEA HS1-0508RH-Q -55 to 125 5962D9569201VEC HS1B-0508RH-Q -55 to 125 5962D9569202VEA HS1-0509RH-Q -55 to 125 5962D9569202VEC HS1B-0509RH-Q -55 to 125 ENABLE -VSUPPLY IN 1 IN 2 IN 3 OUT IN 4 GND +VSUPPLY IN 5 IN 6 IN 7 IN 8 ENABLE -VSUPPLY IN 1A IN 2A IN 3A OUTA IN 4A +VSUPPLY IN 1B IN 2B IN 3B IN 4B OUT B GND Data Sheet August 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

A2 A1 A0 EN “ON” CHANNEL X X X L NONE LLLH 1 LLH H 2 LHLH 3 LHHH 4 HLLH 5 HLHH 6 HHLH 7 HHHH 8 †DIGITAL INPUT LEVEL SHIFT † † † DRIVER DECODER/ IN1 IN2 A0 A1 EN OUT PROTECTION REF IN8 HS-0509RH TRUTH TABLE A1 A0 EN “ON” CHANNEL PAIR X X L NONE LLH 1 LHH 2 HLH 3 HHH 4 †DIGITAL INPUT LEVEL SHIFT † † † DRIVER DECODER/ IN1A IN4A IN1B A0 A1 EN OUT A PROTECTION REF IN4B OUT B HS-0508RH, HS-0509RH

Burn-In/Life Test Circuits HS-0508RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V1 = -15V maximum, -16V minimum V2 = +15V minimum, +16V maximum R1 = 10kΩ ±5% 1/4W C1 = C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D1 = D2 = 1N4002 (or equivalent) F0 = 100kHz 50% duty cycle; VIL = 0.8V max; VIH = 4.0V min. F1 = F0/2 F2 = F1/2 F3 = F2/2 HS-0508RH STATIC BURN-IN TEST CIRCUIT V1 = 5V minimum, 6V maximum V2 = -15V maximum, -16V minimum V3 = +15V minimum, +16V maximum R1 = 10kΩ± 5% 1/4W C1 = C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D1 = D2 = 1N4002 (or equivalent) HS-0509RH DYNAMIC BURN-IN AND LIFE TEST CIRCUIT V2 = +15.5V,±.0.5V V3 = -15.5V,±0.5V R1 = 10kΩ ,±5% C1 = 0.1µF minimum (per socket) D1 = 1N4002 or equivalent (per board) F0 = 100kHz,±10%; F1 = F0/2; F2 = F1/2, 50% duty cycle, VIL = 0.8V max.; VIH = 4.0V min. HS-0509RH STATIC BURN-IN TEST CIRCUIT V1 = +5.5V,±0.5V V2 = +15.5V,±0.5V V3 = -15.5V,±0.5V R1 = 10kΩ , ±10% C1 = 0.1µF minimum (per socket) D1 = 1N4002 or equivalent (per board) D1 C1 D2 C2 D1 C1 D2 C2 V2V3 D1 C1 R1 R1 D1 C1 V2V3 D1 C1 R1 R1 D1 C1 HS-0508RH, HS-0509RH

R1 = R2 = 10kΩ ±5% HS-0508RH R1 = 10kΩ ±5% +5V -15V +1V R1 R2 +1V +15V +5V -15V +1V +1V +15V HS-0508RH, HS-0509RH

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: 81.9mils x 90.2mils x 19mils INTERFACE MATERIALS: Glassivation: Type: Nitride Thickness: 7kÅ ±0.7kÅ Top Metallization: Type: Al Thickness: 16kÅ ±2kÅ Substrate: CMOS Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: < 2.0 x 105 A/cm2 Transistor Count: HS-0508RH 243 HS-0509RH 243 Metallization Mask Layout HS-0508RH HS-0509RH NOTE: Pad numbers correspond to DIP pin numbers only. +VSUP GND OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 EN A0 A1 A2 -VSUP IN 4 IN 2 +VSUP GND OUT A IN 4B IN 3B IN 2B IN 1B IN 3A IN 1A EN A0 A1 -VSUP IN 4A IN 2A OUT B HS-0508RH, HS-0509RH