HS-303ARH INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 3
Technical content
Features
- QML, Per MIL-PRF-38535
- Radiation Performance - Total Dose: 3x10 5 RAD(Si) - SEE: For LET = 60MeV-mg/cm 2 at 60° Incident Angle, <150pC Charge Transferred to the Output of an Off Switch
- No Latch-Up, Dielectrically Isolated Device Islands
- Pinout and Functionally Compatible with Intersil HS-303RH and HI-303 Series Analog Switches
- Analog Signal Range Equal to the Supply Voltage Range
- L o w r (Max, Post-Rad) Pinouts HS1-303ARH, HS-303BRH (SBDIP), CDIP2-T14 TOP VIEW HS9-303ARH, HS-303BRH (FLATPACK) CDFP3-F14 TOP VIEW NC GND IN1 IN2 S2S1 NC GND IN1 IN2 Data Sheet July 7, 2008 FN6411.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
2 FN6411.1 July 7, 2008
Ordering Information
ORDERING NUMBER PART NUMBER TEMP . RANGE (°C) PKG. PKG. DWG. # 5962F9581304QCC HS1-303ARH-8 -55 to +125 14 LD SBDIP D14.3 5962F9581304QXC HS9-303ARH-8 -55 to +125 14 LD Flatpack K14.A 5962F9581304V9A HS0-303ARH-Q -55 to +125 14 Ld SBDIP D14.3 5962F9581304VCC HS1-303ARH-Q -55 to +125 14 LD SBDIP D14.3 5962F9581304VXC HS9-303ARH-Q -55 to +125 14 LD Flatpack K14.A HS0-303ARH/SAMPLE HS0-303ARH/SAMPLE -55 to +125 HS1-303ARH/PROTO HS1-303ARH/PROTO -55 to +125 14 LD SBDIP D14.3 HS9-303ARH/PROTO HS9-303ARH/PROTO -55 to +125 14 LD Flatpack K14.A 5962F9581305QCC HS1-303BRH-8 -55 to +125 14 LD SBDIP D14.3 5962F9581305QXC HS9-303BRH-8 -55 to +125 14 LD Flatpack K14.A 5962F9581305V9A HS0-303BRH-Q -55 to +125 14 LD SBDIP D14.3 5962F9581305VCC HS1-303BRH-Q -55 to +125 14 LD SBDIP D14.3 5962F9581305VXC HS9-303BRH-Q -55 to +125 14 LD Flatpack K14.A HS0-303BRH/SAMPLE HS0-303BRH/SAMPLE -55 to +125 HS1-303BRH/PROTO HS1-303BRH/PROTO -55 to +125 14 LD SBDIP D14.3 HS9-303BRH/PROTO HS9-303BRH/PROTO -55 to +125 14 LD Flatpack K14.A HS-303ARH, HS-303BRH
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6411.1 July 7, 2008 Functional Diagram Die Characteristics DIE DIMENSIONS: 2690µm x 5200µm (106 milsx205 mils) Thickness: 483µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ± 1.0kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ± 2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 196 Metallization Mask Layout HS-303ARH, HS-303BRH N PIN D TRUTH TABLE LOGIC SW1 AND SW2 SW3 AND SW4 0O F F O N 1O N O F F IN1 GND IN2 HS-303ARH, HS-303BRH