HS-302EH INTERSIL | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- QML Class T, Per MIL-PRF-38535
- Radiation Performance -G a m m a D o s e (γ) 1 x 105 RAD(Si)
- No Latch-Up, Dielectrically Isolated Device Islands
- Pin for Pin Compatible with Intersil HI-302 Series Analog Switches
- Analog Signal Range 15V
- L o w R Pin Configurations HS1-302RH, HS1-302EH (SBDIP), CDIP2-T14 TOP VIEW HS9-302RH, HS9-302EH (FLATPACK), CDFP3-F14 TOP VIEW TRUTH TABLE LOGIC ALL SWITCHES 0O F F 1O N N PIN D NC GND IN1 IN2 S2S1 NC GND IN1 IN2 April 1, 2013 FN4603.2 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2013. All Rights Reserved Intersil (and design) and Satellite Applications Flow™ (SAF) are trademarks owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.
HS-302RH, HS-302EH 2 FN4603.2 April 1, 2013
Ordering Information
ORDERING NUMBER PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. # 5962R9581201V9A HS0-302RH-Q -55 to +125 Die N/A 5962R9581202V9A HS0-302EH-Q -55 to +125 Die N/A 5962R9581201QCC HS1-302RH-8 -55 to +125 14 Ld SBDIP D14.3 5962R9581201VCC HS1-302RH-Q -55 to +125 14 Ld SBDIP D14.3 5962R9581202VCC HS1-302EH-Q -55 to +125 14 Ld SBDIP D14.3 5962R9581201QXC HS9-302RH-8 -55 to +125 Flatpack K14.A 5962R9581201VXC HS9-302RH-Q -55 to +125 Flatpack K14.A 5962R9581202VXC HS9-302EH-Q -55 to +125 Flatpack K14.A HS9-302RH/PROTO HS9-302RH/PROTO -55 to +125 Flatpack K14.A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
HS-302RH, HS-302EH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4603.2 April 1, 2013 For additional products, see www.intersil.com/en/products.html Die Characteristics DIE DIMENSIONS: (2130µm x 1930µm x 533µm ±25.4µm) 84 x 76 x 21mils ±1mil METALLIZATION: Type: Al Thickness: 12.5kÅ ±2kÅ SUBSTRATE POTENTIAL: Unbiased (DI) BACKSIDE FINISH: Silicon PASSIVATION: Type: Silox (SiO2) Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: PROCESS: Metal Gate CMOS, Dielectric Isolation Metallization Mask Layout HS-302RH, HS-302EH IN1 NC GND IN2