HS-26C32RH-T INTERSIL | Alldatasheet
Document overview
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- PDF pages: 3
Technical content
Features
- QML Class T, Per MIL-PRF-38535
- Radiation Performance
- EIA RS-422 Compatible Inputs
- CMOS Compatible Enable Inputs
- Input Fail Safe Circuitry
- High Impedance Inputs when Disabled or Powered Down
- Low Power Dissipation 138mW Standby (Max)
- Single 5V Supply
- F u l l - 5 5 oC to 125oC Military Temperature Range Pinouts HS1-26C32RH-T (SBDIP), CDIP2-T16 TOP VIEW HS9-26C32RH-T (FLATPACK), CDFP4-F16 TOP VIEW
Ordering Information
TEMP. RANGE (oC) 5962R9568901TEC HS1-26C32RH-T -55 to 125 HS1-26C32RH/Proto HS1-26C32RH/Proto -55 to 125 5962R9568901TXC HS9-26C32RH-T -55 to 125 HS9-26C32RH/Proto HS9-26C32RH/Proto -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. AIN AIN AOUT ENABLE COUT CIN GND CIN VDD BIN BOUT ENABLE DOUT DIN DIN BIN AIN AIN AOUT ENABLE COUT CIN CIN GND 11 6 VDD BIN BIN BOUT ENABLE DOUT DIN DIN Data Sheet July 1999 FN4592.1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved Satellite Applications Flow™ (SAF) is a trademark of Intersil Corporation.
ON 1 X VID ≥ VTH (Max) 1 ON 1 X VID ≤ VTH (Min) 0 ON X 0 VID ≥ VTH (Max) 1 ON X 0 VID ≤ VTH (Min) 0 ON 1 X Open 1 ON X 0 Open 1 ENABLE ENABLE AOUTBOUTCOUT DIN DOUT DIN CIN CIN BIN BIN AIN AIN +-+-+-+- HS-26C32RH-T
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Die Characteristics DIE DIMENSIONS: 2140µm x 3290µm x 533µm ±25.4µm (85 x 130 x 21mils ±1mil) METALLIZATION: M1: Mo/Tiw Thickness: 5800Å M2: Al/Si/Cu Thickness: 10kÅ ±1kÅ SUBSTRATE POTENTIAL: Internally connected to VDD. May be left floating. BACKSIDE FINISH: Silicon PASSIVATION: Type: SiO2 Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 315 PROCESS: Radiation Hardened CMOS, AVLSI Metallization Mask Layout HS-26C32RH AIN VDD BIN AIN (2) AOUT (3) ENAB (4) COUT (5) CIN (6) (8) (9) (14) BIN (13) BOUT (12) ENAB (11) DOUT (10) DIN (1) (16) (15) (7) CIN GND DIN HS-26C32RH-T