HS-2400RH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically Screened to SMD # 5962-95684
  • QML Qualified per MIL-PRF-38535 Requirements
  • Digital Programmability
  • High Rate Slew
  • Wide Gain Bandwidth
  • Single Capacitor Compensation for Unity Gain
  • DTL/TTL Compatible Inputs

Applications

  • Signal Selection/Multiplexing
  • Operational Amplifier Gain Stage
  • Oscillator Frequency
  • Filter Characteristics
  • Add-Subtract Functions
  • Integrator Characteristics
  • Comparator Levels Pinout

16 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

(CERDIP) MIL-STD-1835 GDIP-T16 TOP VIEW

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962D9568401VEA HS1-2400RH-Q -55 to 125 14 OUTPUT AMP ENABLE GND COMP OUT +IN3 -IN3 +IN4 -IN4 -IN1 +IN1 +IN2 -IN2 DECODE CONTROL Data Sheet September 1999 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. www.intersil.com or 321-724-7143| Copyright © Intersil Corporation 1999

0.002 S31 S51 S61 100 10K 0.002 S41 100 10K 0.002 S32 S52 S62 100 10K 0.002 S42 100 10K 0.002 S33 S53 S63 100 10K 0.002 S43 100 10K 0.002 S34 S54 S64 100 10K 0.002 S44 DUT VIN S7 1 S8V5 200 OPEN OPEN OPEN OPEN 4.9K 47pF 1 µF 91 1 47pF1µF 15pF S14 S11 OPEN ACOUT 50pF 500K --1 10+ - FB 50K (NOTE 1) NOTES: 1. For loop stability, use Min value capacitor to prevent oscillation. 2. Includes stray capacitance. 3. All capacitors =±10% (µF). 4. All resistors =±1% (Ω ). 5. DUT pin numbers refer to 14 pin CERDIP Package. (NOTE 2) OUT E HS-2400RH

NOTES: 6. R1 = 100kΩ ,/Socket, 5%, 1/4W (Min). 7. C1 = C2 = 0.01µF/Socket (Min) or 0.1µF/Row (Min). 8. C3 = 0.001µF/Socket, 10%. 9. D1 = D2 = 1N4002 or equivalent (per board). 11. Duty Cycle 50% for: f0 = 100kHz, f1 = 50kHz, f2 = 25kHz. Test Waveforms SLEW RATE WAVEFORMS OVERSHOOT, RISE AND FALL TIME WAVEFORMS INPUT +SR +5.0V -5.0V -5.0V +5.0V -SR OUTPUT +5.0V -5.0V -5.0V +5.0V ∆T∆T ∆TSR =∆T ∆V∆V INPUT tR , +OS +200mV 0V -200mV tF, -OS OUTPUT VPEAK 0V -200mV tR 90% 10% VFINAL = +200mV 10% tF VPEAK 90% OUTPUT AMP ENABLE GND COMP OUT V-2 DECODE CONTROL D2 C2 D1 C1 HS-2400RH

NOTES: 12. V1 = +15V. 13. V2 = -15V. 14. R = 1 MegΩ. 15. C = 0.1µF. Schematic Diagram NOTE: 16. Diagram Includes: One Input Stage, Decode Control, Bias Network, and Output Stage. GND C R GND R R GND C ENABLE GND OUT 2.4K 22.9K 1.6K 1.8K 8.0K 2.0KR35 1.6K R7 5.6K Q10 Q11 Q13Q12 Q15 Q14 Q16 1.5K R10 10K R11 10K VA VC Q17 VB Q18 Q19 Q20 VD R12 1.6K Q28VE R13 0.8K Q22 R15 10K R16 10K Q21 Q26Q27 R14 10K Q29 Q23 Q24 Q25 Q30 Q32 Q33 Q102 Q34 Q38 R18 2.0K Q103 Q35 Q31 Q36 Q37 Q39 Q40 Q41 Q79 Q81 Q82 Q84 Q80 Q83 Q86 Q89 Q88 R35 0.75K Q85 Q98 Q92R30 1.2K 9.0pF Q93 Q42 R19 1.6K TO ADDITIONAL INPUT STAGES R29 0.4K Q90 Q91 R33 4K Q97 Q100 Q99 Q95Q94 +VCC -VEE R31 36.5 R32 Q96 COMPIN-IN+ D1D0 R17 1.6K Q87 R34 1.6K Q101 HS-2400RH

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Die Characteristics DIE DIMENSIONS: 88 mils x 67 mils x 19 mils±1 mils 2240µm x 1710µm x 483µm ±25.4µm INTERFACE MATERIALS: Top Metallization: Type: Al, 1% Cu Thickness: 16kÅ ±2kÅ Glassivation: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.). Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ Substrate: Potential (Powered Up) Unbiased ADDITIONAL INFORMATION: Worst Case Current Density: < 2 x 105A/cm2 Transistor Count: 251 Process: Bipolar Dielectric Isolation Metallization Mask Layout HS-2400RH +IN3 D1ENABLEGNDCOMPV+OUT +IN2 -IN2 +IN1 -IN1 -IN4 +IN4 -IN3 HS-2400RH