HS-1840ARH-T INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 3
Technical content
Features
- QML Class T, Per MIL-PRF-38535
- Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - No Latch-Up, Dielectrically Isolated Device Islands
- Improved rDS(ON) Linearity
- Improved Access Time 1.5µs (Max) Over Temp and Rad
- High Analog Input Impedance 500MΩ During Power Loss (Open)
- ±35V Input Over Voltage Protection (Power On or Off)
- Excellent in Hi-Rel Redundant Systems
- Break-Before-Make Switching Pinouts HS1-1840ARH-T (SBDIP), CDIP2-T28 TOP VIEW HS9-1840ARH-T (FLATPACK) CDFP3-F28 TOP VIEW
Ordering Information
TEMP. RANGE (oC) 5962R9563002TXC HS1-1840ARH-T -55 to 125 HS1-1840ARH/Proto HS1-1840ARH/Proto -55 to 125 5962R9563002TYC HS9-1840ARH-T -55 to 125 HS9-1840ARH/Proto HS9-1840ARH/Proto -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. +V S NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5V S) VREF ADDR A3 OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 -VS IN 4 IN 2 S NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5V S) VREF ADDR A3 OUT -VS IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 Data Sheet July 1999 File Number 4589.1
A3 A2 A1 A0 EN “ON” CHANNEL XXXXH None LLLLL 1 LLLHL 2 LLHLL 3 LLH HL 4 LHLLL 5 LHLHL 6 LHHLL 7 LHHHL 8 HLLLL 9 HLLHL 1 0 HLHLL 1 1 HLHHL 1 2 H HLLL 1 3 HHLHL 1 4 HHHL L 1 5 HHHHL 1 6 P EN IN 1 OUT IN 16 DIGITAL ADDRESS DECODERSADDRESS INPUT BUFFER AND LEVEL SHIFTER MULTIPLEX SWITCHES P HS-1840ARH-T
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Die Characteristics DIE DIMENSIONS: (2820µm x 4080µm x 483µm ±25.4µm) 111 x 161 x 19mils±1mil METALLIZATION: Type: Al Si Cu Thickness: 16.0kÅ ±2kÅ SUBSTRATE POTENTIAL: Unbiased (DI) BACKSIDE FINISH: Silicon PASSIVATION: Type: Nitride (Si3N 4) over Silox (SiO 2) Nitride Thickness: 4.0kÅ ±0.5kÅ Silox Thickness: 12.0kÅ ±1.3kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: 407 PROCESS: Radiation Hardened Silicon Gate, Dielectric Isolation Metallization Mask Layout HS-1840ARH-T IN7 IN6 IN5 IN4 IN3 IN2 IN1 ENABLE VREF GND IN8 OUT IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9 HS-1840ARH-T