HS-1840ARH INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 7
Technical content
Features
- Electrically Screened to SMD # 5962-95630
- QML Qualified per MIL-PRF-38535 Requirements
- Pin-to-Pin for Intersil’s HS-1840RH and HS-1840/883S
- Improved Radiation Performance - Gamma Dose ( γ) 3x10 5RAD(Si)
- I m p r o v e d rDS(ON) Linearity
- Improved Access Time 1.5µs (Max) Over Temp and Post Rad
- High Analog Input Impedance 500MΩ During Power Loss (Open)
- ±35V Input Overvoltage Protection (Power On or Off)
- Dielectrically Isolated Device Islands
- Excellent in Hi-Rel Redundant Systems
- Break-Before-Make Switching
- N o L a t c h - U p
Ordering Information
MKT. NUMBER TEMP. RANGE (°C) PART MARKING NO. PACKAGE 5962F9563002QXC HS1-1840ARH-8 -55 to +125 Q 5962F95 63002QXC 28 Ld SBDIP 5962F9563002QYC HS9-1840ARH-8 -55 to +125 Q 5962F95 63002QYC 28 Ld Flatpack 5962F9563002VXC HS1-1840ARH-Q -55 to +125 Q 5962F95 63002VXC 28 Ld SBDIP 5962F9563002VYC HS9-1840ARH-Q -55 to +125 Q 5962F95 63002VYC 28 Ld Flatpack HS1-1840ARH/PROTO HS1-1840ARH/PROTO -55 to +125 HS1- 1840ARH /PROTO 28 Ld SBDIP HS9-1840ARH/PROTO HS9-1840ARH/PROTO -55 to +125 HS9- 1840ARH /PROTO 28 Ld Flatpack HS1-1840ARH-T HS1-1840ARH-T -55 to +125 Q 5962R95 63002TXC 28 Ld SBDIP 5962F9563002V9A HS0-1840ARH-Q -55 to +125 5962F9563003QXC HS1-1840BRH-8 -55 to +125 Q 5962F95 63003QXC 28 Ld SBDIP CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2002, 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. September 14, 2010 FN4355.3
HS-1840ARH, HS-1840BRH 2 FN4355.3 September 14, 2010 Pin Configurations 5962F9563003QYC HS9-1840BRH-8 -55 to +125 Q 5962F95 63003QYC 28 Ld Flatpack 5962F9563003VXC HS1-1840BRH-Q -55 to +125 Q 5962F95 63003VXC 28 Ld SBDIP 5962F9563003VYC HS9-1840BRH-Q -55 to +125 Q 5962F95 63003VYC 28 Ld Flatpack HS1-1840BRH/PROTO HS1-1840BRH/PROTO -55 to +125 HS1- 1840BRH /PROTO 28 Ld SBDIP HS9-1840BRH/PROTO HS9-1840BRH/PROTO -55 to +125 HS9- 1840BRH /PROTO 28 Ld Flatpack 5962F9563003V9A HS0-1840BRH-Q -55 to +125 HS1-1840ARH, HS1-1840BRH (28 LD SBDIP) CDIP2-T28 TOP VIEW HS9-1840ARH, HS9-1840BRH (28 LD FLATPACK) CDFP3-F28 TOP VIEW Ordering Information (Continued) ORDERING NUMBER INTERNAL MKT. NUMBER TEMP. RANGE (°C) PART MARKING NO. PACKAGE +VS NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5V S) VREF ADDR A3 OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2 -VS IN 4 IN 2 S NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND (+5V S) VREF ADDR A3 OUT -VS IN 8 IN 7 IN 6 IN 5 IN 4 IN 3 IN 2 IN 1 ENABLE ADDR A0 ADDR A1 ADDR A2
TABLE 1. TRUTH TABLE
FIGURE 1. DYNAMIC BURN-IN AND LIFE TEST CIRCUIT FIGURE 2. .STATIC BURN-IN TEST CIRCUIT
- The above test circuits are utilized for all package types.
- The Dynamic Test Circuit is utilized for all life testing.
- All irradiation testing is performed in the 28 lead CERDIP package.
C1 = C2 = 0.01µF ±10%, 1 EACH PER SOCKET, MINIMUM. D1 = D2 = 1N4002, 1 EACH PER BOARD, MINIMUM. SQUARE WAVE, 50% DUTY CYCLE, 0V TO 15V PEAK ±10%. C1 = C2 = 0.01µF MINIMUM, 1 EACH PER SOCKET, MINIMUM.
HS-1840ARH, HS-1840BRH 5 FN4355.3 September 14, 2010 Die Characteristics DIE DIMENSIONS: (2820µmx4080µm x 483µm ±25.4μm) 111 milsx161 milsx19 mils ±1 mil INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorus Silicon Glass) Thickness: 8.0k Å ±1kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ±2kÅ Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: Modified SEM Transistor Count: 407 Process: Radiation Hardened Silicon Gate, Bonded Wafer, Dielectric Isolation Metallization Mask Layout HS-1840ARH, HS-1840BRH IN7 IN6 IN5 IN4 IN3 IN2 IN1 ENABLE VREF GND IN8 OUT IN16 IN15 IN14 IN13 IN12 IN11 IN10 IN9
HS-1840ARH, HS-1840BRH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accura te and reliable. However, no re sponsibility is assumed by Inte rsil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4355.3 September 14, 2010 For additional products, see www.intersil.com/product_tree Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 4. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 5. The maximum limits of lead dimensions b and c or M shall be mea- sured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 6. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 7. Corner leads (1, N, N/2, and N/2+1) may be configured with a par- tial lead paddle. For this configur ation dimension b3 replaces di- mension b2. 8. Dimension Q shall be measured from the seating plane to the base plane. 9. Measure dimension S1 at all four corners. 10. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 11. N is the maximum number of terminal positions. 12. Braze fillets shall be concave. 13. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 14. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D28.6 MIL-STD-1835 CDIP2-T28 (D-10, CONFIGURATION C)
28 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
A - 0.232 - 5.92 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.500 0.610 12.70 15.49 - e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N2 8 2 8 8 Rev. 0 5/18/94
HS-1840ARH, HS-1840BRH 7 FN4355.3 September 14, 2010 Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-cent er lid, meniscus, and glass over- run. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the me- niscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-
0.004 H A - BM DS S
-A- -B-
0.036 H A - BM DS S
e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K28.A MIL-STD-1835 CDFP3-F28 (F-11A, CONFIGURATION B)
28 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.740 - 18.80 3 E 0.460 0.520 11.68 13.21 - E1 - 0.550 - 13.97 3 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.00 - 0.00 - 6 N2 8 2 8- Rev. 0 5/18/94