HS-139EH INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- QML Qualified Per MIL-PRF-38535 Requirements
- Radiation Environment - Latch-up Free Under any Conditions - Low Dose Rate Effects Immunity
- 100V Output Voltage Withstand Capability
- ESD Protection to >3000V
- Differential Input Voltage Range Equal to the Supply Voltage
- Pb-Free (RoHS Compliant)
Applications
- P u l s e G e n e r a t o r s
- Timing Circuitry
- Level Shifting
- Analog-to-Digital Conversion
Ordering Information
(Note) INTERNAL MKT. NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PACKAGE DRAWING NUMBER 5962F9861303VCC HS1-139EH-Q Q 5962F98 61303VCC -55 to +125 14 Ld SBDIP D14.3 5962F9861301VCC HS1-139RH-Q Q 5962F98 61301VCC -55 to +125 14 Ld SBDIP D14.3 5962F9861301QCC HS1-139RH-8 Q 5962F98 61301QCC -55 to +125 14 Ld SBDIP D14.3 HS1-139RH/PROTO HS1-139RH/PROTO HS1-139RH/PROTO -55 to +125 14 Ld SBDIP D14.3 5962F9861301VXC HS9-139RH-Q Q 5962F98 61301VXC -55 to +125 14 Ld FLATPACK K14.A 5962F9861301QXC HS9-139RH-8 Q 5962F98 61301QXC -55 to +125 14 Ld FLATPACK K14.A 5962F9861302VXC HS9-139EH-Q Q 5962F98 61302VXC -55 to +125 14 Ld FLATPACK K14.A HS9-139RH/PROTO HS9-139RH/PROTO HS9-139RH /PROTO -55 to +125 14 Ld FLATPACK K14.A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 1999, 2004, 2008, 2009, 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. July 12, 2012 FN3573.5
HS-139RH, HS-139EH 2 FN3573.5 July 12, 2012 Pin Configurations s HS-139RH, HS-139EH (SBDIP CDIP2-T14) TOP VIEW HS-139RH, HS-139EH (FLATPACK CDFP3-F14) TOP VIEW Die Characteristics DIE DIMENSIONS: 3750µm x 2820µm (148 mils x 111 mils) 483µm ±25.4µm (19 mils ±1 mil) INTERFACE MATERIALS: Glassivation: Type: Silox (SiO2) Thickness: 8.0kÅ ±1.0kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ±2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: OUT 2 OUT 1 - IN 1 + IN 1 - IN 2 + IN 2 OUT 3 OUT 4 GND + IN 4 - IN 4 + IN 3 - IN 3 1OUT 2 OUT 1 - IN 1 + IN 1 - IN 2 +IN 2 OUT 3 OUT 4 GND + IN 4 - IN 4 + IN 3 - IN 3
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 1. HS-139RH, HS-139EH PAD COORDINATES