HS-0506RH INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 14

Technical content

Features

  • Low On Resistance 400Ω Max
  • Wide Analog Signal Range ±15V
  • TTL/CMOS Compatible 2.4V (Logic “1”)
  • Access Time 1000ns Max
  • 44V Maximum Power Supply
  • Break-Before-Make Switching
  • No Latch-up
  • Gamma Dose 1 x 10

4 RAD (Si)

Applications

  • Data Acquisition Systems
  • Precision Instrumentation
  • Demultiplexing
  • Selector Switch

Ordering Information

HS1-0506RH-Q -55 oC to 125oC 28 Lead CerDIP HS1-0507RH-Q -55 oC to 125oC 28 Lead CerDIP September 1997 Spec Number 518860 File Number 4028.1 Pinouts HS-0506RH 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835 GDIP1-T28 TOP VIEW HS-0507RH 28 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE (CerDIP) MIL-STD-1835 GDIP1-T28 TOP VIEW VSUPPLY NC NC IN 16 IN 15 IN 14 IN 13 IN 12 IN 11 IN 10 IN 9 GND NC ADDRESS A3 OUT IN 8 IN 7 IN 6 IN 5 IN 3 IN 1 ENABLE ADDRESS A0 ADDRESS A1 ADDRESS A2 -VSUPPLY IN 4 IN 2 +VSUPPLY OUT B NC IN 8B IN 7B IN 6B IN 5B IN 4B IN 3B IN 2B IN 1B GND NC NC OUT A IN 8A IN 7A IN 6A IN 5A IN 3A IN 1A ENABLE ADDRESS A0 ADDRESS A1 ADDRESS A2 -VSUPPLY IN 4A IN 2A DB NA NOT RECOMMENDED FOR NEW DESIGNS See HS-0546RH, HS-0547RH contact our Technical Service Center at 1-888-INTERSIL or www.intersil.com/tsc

HS-0506RH, HS-0507RH Spec Number 518860 HS-0506RH TRUTH TABLE A3 A2 A1 A0 EN “ON” CHANNEL XXXXL N O N E LLLLH 1 LLLH H 2 LLHLH 3 L LHHH 4 LHLLH 5 LHLHH 6 LHHLH 7 LHHHH 8 HLLLH 9 HLLHH 1 0 HLHLH 1 1 HLHHH 1 2 HHL LH 1 3 HHLHH 1 4 HHHLH 1 5 HHHHH 1 6 HS-0507RH TRUTH TABLE A2 A1 A0 EN “ON” CHANNEL PAIR XXXL N O N E LLLH 1 LLH H 2 LHLH 3 LHHH 4 HLLH 5 HLHH 6 HHLH 7 HHHH 8 Functional Diagrams HS-0506RH HS-0507RH † DIGITAL INPUT REF † † † † DRIVER DECODER/ IN1 IN2 IN16 A1 A2 A3 EN OUT PROTECTION LEVEL SHIFT † † † A1 A2 EN IN1B † DIGITAL INPUT LEVEL SHIFT REF IN1A IN8A IN8B OUT A DRIVER DECODER/ OUT B PROTECTION

of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified.

  1. Use for forcing conditions for all DC tests unless otherwise specified.

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. The parameters listed in this table are controlled via desi gn or process parameters and are not directly tested. These parameters are

characterized upon initial design release and upon design changes which would affect these characteristics.

  1. Worst case isolation occurs on channel 8B due to proximity of the output pins.

Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified.

Specifications HS-0506RH, HS-0507RH Negative Supply Current I(-) VA = 0V, VEN = 2.4V +25 oC- 1 . 0 - m A Standby Positive Supply Current +ISBY VA = 0V, VEN = 0V +25 oC- 3 . 0 m A Standby Negative Supply Current -ISBY VA = 0V, VEN = 0V +25 oC- 1 . 0 - m A Switch “ON” Resistance +RDS1 VS = +10V, ID = +1mA +25 oC - 400 Ω -RDS1 VS = -10V, ID = -1mA +25 oC - 400 Ω Logic Level Voltage VAL Note 1 +25 oC- 0 . 8 V VAH Note 1 +25 oC2 . 4 - V NOTE: 1. Use for forcing conditions for all DC tests unless otherwise specified. TABLE 4B. POST 10K RAD AC ELECTRICAL PERFORMANCE CHARACTERISTICS Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. PARAMETERS SYMBOL CONDITIONS TEMPERATURE LIMITS UNITSMIN MAX Propagation Delay Times: Address Inputs to I/O Channel Times tA RL = 10M Ω +25oC - 1000 ns Enable to I/O tON(EN) RL = 200 Ω +25oC - 1000 ns tOFF(EN) RL = 200 Ω +25oC - 1000 ns TABLE 4A. POST 10K RAD DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device tested at +VSUPPLY = +15V. -VSUPPLY = -15V, VEN = 2.4V, Unless Otherwise Specified. PARAMETERS SYMBOL CONDITIONS TEMPERATURE LIMITS UNITSMIN MAX Spec Number 518860

TABLE 5. BURN-IN DELTA PARAMETERS (T A = +25oC) TABLE 6. APPLICABLE SUBGROUPS

  1. Alternate Group A testing in accordance with MIL-STD-883 Method 5005 may be exercised.

HS-0506RH, HS-0507RH Spec Number 518860 Intersil Space Level Product Flow -Q Wafer Lot Acceptance (All Lots) Method 5007 (Includes SEM) (Note 1) GAMMA Radiation Verification (Each Wafer) Method 1019,

4 Samples/Wafer, 0 Rejects

100% Nondestructive Bond Pull, Method 2023 Sample - Wire Bond Pull Monitor, Method 2011 Sample - Die Shear Monitor, Method 2019 or 2027 100% Internal Visual Inspection, Method 2010, Condition A 100% Temperature Cycle, Method 1010, Condition C,

10 Cycles

100% Constant Acceleration, Method 2001, Condition per Method 5004 100% PIND, Method 2020, Condition A 100% External Visual 100% Serialization 100% Initial Electrical Test (T0) 100% Static Burn-In, Condition A or B, 72 hrs. min., +125 oC min., Method 1015 100% Interim Electrical Test 1 (T1) 100% Delta Calculation (T0-T1) 100% PDA 1, Method 5004 (Note 2) 100% Dynamic Burn-In, Condition D, 240 hrs., +125 oC or Equivalent, Method 1015 100% Interim Electrical Test 2 (T2) 100% Delta Calculation (T0-T2) 100% PDA 2, Method 5004 (Note 2) 100% Final Electrical Test 100% Fine/Gross Leak, Method 1014 100% Radiographic (X-Ray), Method 2012 (Note 3) 100% External Visual, Method 2009 Sample - Group A, Method 5005 (Note 4) Sample - Group B, Method 5005 (Note 5) Sample - Group D, Method 5005 (Notes 5 and 6) 100% Data Package Generation (Note 7) NOTES: 1. Modified SEM Inspection, not compliant to MIL-STD-883, Method 2018. This device does not meet the Class S minimum metal step coverage of 50%. The metal does meet the current density requirement of <2 E5 A/cm2. Data provided upon request. 2. Failures from subgroup 1 and deltas are used for ca lculating PDA. The maximum allowable PDA = 5%. 3. Radiographic (X-Ray) inspection may be performed at any point after serialization as allowed by Method 5004. 4. Alternate Group A testing may be performed as allowed by MIL-STD-883, Method 5005. separate line items for Group B test, Group B samples, Group D test and Group D samples. 6. Group D Generic Data, as defined by MIL-I-38535, is optional a nd will not be supplied unless required by the P.O. When required, the P.O. should include a separate line item for Group D generic da ta. Generic data is not guaranteed to be available and is theref ore not available in all cases. 7. Data Package Contents:

  • Cover Sheet (Intersil Name and/or Logo, P.O. Number, Customer Part Number, Lot Date Code, Intersil Part Number, Lot Number, Quantity).
  • Wafer Lot Acceptance Report (Method 5007). Includes reproductions of SEM photos with percent of step coverage.
  • GAMMA Radiation Report. Contains Cover page, disposition, Rad Dose, Lot Number, Test Package used, Specification Numbers, Test equipment, etc. Radiation Read and Record data on file at Intersil.
  • X-Ray report and film. Includes penetrometer measurements.
  • Screening, Electrical, and Group A attributes (Screening attributes begin after package seal).
  • Lot Serial Number Sheet (Good units serial number and lot number).
  • Variables Data (All Delta operations). Data is identified by serial number. Data header includes lot number and date of test.
  • Group B and D attributes and/or Generic data is included when required by the P.O.
  • The Certificate of Conformance is a part of the shipping invoice and is not part of the Data Book. The Certificate of Conformance is signed by an authorized Quality Representative.

HS-0506RH, HS-0507RH Test Circuits INPUT LEAKAGE CURRENT ID(OFF) IS(OFF) ID(ON) SUPPLY CURRENTS CHARGE TRANSFER ERROR RDS OFF CHANNEL ISOLATION CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VAL = 0.8V; VAH = 2.4V UNUSED INPUTS TO GND IIL IIH IIL IIH IIL IIH CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VA = VEN = 0.8V VDVS ID (OFF) TRUTH TABLE VAL = 0.8V; VAH = 2.4V CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VDVS IS (OFF) 0.8V TRUTH TABLE VAL = 0.8V VAH = 2.4V CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VDVS 2.4V ID (ON) CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VA = 0V VEN = 2.4V VEN = 0V I(-) -SBY I(+) +SBY VGEN CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT 5.0V 0.01µF TEST POINT TRUTH TABLE VAL = 0.8V; VAH = 2.4V CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT VS 2.4V RDN = VM IDVM ID CH 1 V+ GND V- CH 2 CH 3 CH n AN ENA0 OUT 0.8V 15µF(1) CH 4 CH 5 CH 6 CH 7 VS OUT 1KΩ (1) INCLUDES ALL FACTORS AND SCOPE OR VOLTMETER CAPACITANCE Spec Number 518860

HS-0506RH, HS-0507RH Burn-Circuits DYNAMIC V1 = +15V minimum, +16V maximum V2 = -15V maximum, -16V minimum R1, R2 = 10kΩ, ± 5%, 1/4 or 1/2W (per socket) C1, C2 = 0.01µF minimum (per socket) or 0.1µF minimum (per row) D1, D2 = 1N4002 or equivalent (per board) F0 = 100kHz, 10%; F1 = F0/2; F2 = F1/2; F3 = F2/2; F4 = F3/2 40% - 60% duty cycle; VIL = 0.8V maximum; VIH = 4.0V minimum NOTES: 1. The above test circuits are utilized for all package types. 2. The dynamic test circuit is utilized for all life testing. STATIC V1 = +5V minimum, +6V maximum V2 = +15V minimum, +16V maximum V3 = -15V maximum, -16V minimum R1, R2 = 10kΩ, ± 5%, 1/4 or 1/2W (per socket) C1, C2 =0.01µF minimum (per socket) or 0.1µF minimum (per row) D1, D2 = 1N4002 or equivalent (per board) D2 C2 V2R2 D1C1 D2 C2 V3R2 D1C1 Spec Number 518860 Irradiation Circuit 10kΩ +15V +1V +5V NC -15V 10kΩ

HS-0506RH, HS-0507RH Metallization Topology DIE DIMENSIONS: 82 x 129 x 19 mils METALLIZATION: Type: Al Thickness: 16k Å ± 2kÅ GLASSIVATION: Type: Nitride Thickness: 7kÅ ± 0.7kÅ WORST CASE CURRENT DENSITY: < 2.0 x 105 A/cm2 TRANSISTOR COUNT: HS-0506RH 421 HS-0507RH 421 PROCESS: CMOS-DI Metallization Mask Layout NOTE: Pad numbers correspond to DIP pin numbers only. HS-0506RH HS-0507RH Spec Number 518860