HS0-RTX2010RH-Q

HS-RTX2010RH INTERSIL | Alldatasheet

Document overview

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• PDF pages: 36

Technical content

Features

• Electrically Screened to SMD # 5962-95635
• QML Qualified per MIL-PRF-38535 Requirements
• Fast 125ns Machine Cycle
• 1.2µM TSOS4 CMOS/SOS Process
• Single Event Upset Error Rate . . . . <1 x 10-10 Errors/Bit-Day (Note)
• -55oC - 125oC, 5V±10% Operation
• Single Cycle Instruction Execution
• Fast Arithmetic Operations - Single Cycle 16-Bit Multiply - Single Cycle 16-Bit Multiply Accumulate - Single Cycle 32-Bit Barrel Shift - Hardware Floating Point Support
• C Software Development Environment
• Direct Execution of Fourth Language
• Single Cycle Subroutine Call/Return
• Four Cycle Interrupt Latency
• On-Chip Interrupt Controller
• Three On-Chip 16-Bit Timer/Counters
• Two On-Chip 256 Word Stacks
• ASIC Bus™ for Off-Chip Architecture Extension
• 1 Megabyte Total Address Space
• Word and Byte Memory Access
• Fully Static Design - DC to 8MHz Operation
• 84 Lead Quad Flat Package or 85 Pin Grid Array
• Third Party Software and Hardware Development Systems NOTE: Single Event Upset error rates are Adams 10% worst case environment under worst case conditions for upset.

Applications

• Space Systems Embedded Control
• Digital Filtering
• Image Processing
• Scientific Instrumentation
• Optical Systems
• Control Systems
• Attitude/Orbital Control

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962F9563501QXC HS8-RTX2010RH-8 55 to 125 5962F9563501QYC HS9-RTX2010RH-8 55 to 125 5962F9563501V9A HS0-RTX2010RH-Q 25 5962F9563501VXC HS8-RTX2010RH-Q 55 to 125 5962F9563501VYC HS9-RTX2010RH-Q 55 to 125 HS8-RTX2010RH/Proto HS8-RTX2010RH/Proto 55 to 125 HS9-RTX2010RH/Proto HS9-RTX2010RH/Proto 55 to 125 Data Sheet March 2000 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143| Copyright © Intersil Corporation 2000 Real Time Express™, RTX™, and ASIC Bus™ are trademarks of Intersil Corporation.

NOTE: An overbar on a signal name represents an active LOW signal. BAC D E F G H J K L GA00 MD14 MD12 MD11 MD08 INTA TCLK E I5 GD15 MD05 GND GND MD04 MD03 MD02 GD07 MD00 NEW MD01 VDD LDS UDS GND MA18 GND MA04 MA08 GD05 MA10 MA13 MA15 MA17 MA19 MA05 MA07 GD04 MA09 MA12 VDD MA14 MA16 MA06 MA11 GNDGD09 BOOT PCLK GD01 MA01 GA01 VDD MD06 GA02 ICLK MD15 MD13 MD10 MD09 MD07 NMI GND ABC D EFG HJK L VDD MA02 MA03E I1 E I2 GD14 GD11 GD10E I4 E I3 WAIT GD13 GD12 GD06 GD03 GD02 GD00GD08 INT- SUP

2 RESET

ALIGN. PIN HS-RTX2010RH

(LEAD LENGTH NOT TO SCALE) SEE INTERSIL OUTLINE R84.A Pinouts (Continued) NOTE: An overbar on a signal name represents an active LOW signal. HS-RTX2010RH TOP VIEW MD02 MD03 MD04 GND MD05 MD06 MD07 VDD MD08 MA17 MA18 MA19 GND LDS UDS NEW BOOT PCLK MD00 MD01 EI5 MD09 MD10 MD11 MD12 MD13 MD14 GND MD15 GA00 GA01 GA02 TCLK INTA NMI INTSUP VDD EI1 EI2 EI3 EI4 MA04 MA03 MA02 MA01 GD00 GD01 GD02 MA16 MA15 MA14 MA13 VDD MA12 MA11 MA10 MA09 GND MA08 MA07 MA06 MA05 RESET WAIT ICLK GD14 GD13 GND GD12 GD11 GD10 GD09 GD08 GD07 VDD GD06 GD05 GD04 GD03 GND GD15 GR/W GIO MR/ W PGA And CQFP Pin/Signal Assignments CQFP PGA PIN SIGNAL NAME TYPE

1 C6 GA02 Output; Address Bus

2 A6 TCLK Output

3 A5 INTA Output

4 B5 NMI Input

5 C5 INTSUP Input

6 A4 VDD Power

7 B4 EI1 Input

8 A3 EI2 Input

9 A2 EI3 Input

10 B3 EI4 Input

11 A1 EI5 Input

12 B2 RESET Input

13 C2 WAIT Input

14 B1 ICLK Input

15 C1 GR/W Output

16 D2 GIO Output

17 D1 GD15 I/O; Data Bus

18 E3 GD14 I/O; Data Bus

19 E2 GD13 I/O; Data Bus

20 E1 GND Ground

21 F2 GD12 I/O; Data Bus

22 F3 GD11 I/O; Data Bus

23 G3 GD10 I/O; Data Bus

24 G1 GD09 I/O; Data Bus

25 G2 GD08 I/O; Data Bus

26 F1 GD07 I/O; Data Bus

27 H1 VDD Power

28 H2 GD06 I/O; Data Bus

29 J1 GD05 I/O; Data Bus

30 K1 GD04 I/O; Data Bus

31 J2 GD03 I/O; Data Bus

32 L1 GND Ground

33 K2 GD02 I/O; Data Bus

34 K3 GD01 I/O; Data Bus

35 L2 GD00 I/O; Data Bus

36 L3 MA01 Output; Address Bus

37 K4 MA02 Output; Address Bus

38 L4 MA03 Output; Address Bus

39 J5 MA04 Output; Address Bus

40 K5 MA05 Output; Address Bus

41 L5 MA06 Output; Address Bus

42 K6 MA07 Output; Address Bus

43 J6 MA08 Output; Address Bus

44 J7 GND Ground

45 L7 MA09 Output; Address Bus

46 K7 MA10 Output; Address Bus

Pin/Signal Assignments (Continued) CQFP PGA PIN SIGNAL NAME TYPE HS-RTX2010RH

47 L6 MA11 Output; Address Bus

48 L8 MA12 Output; Address Bus

49 K8 MA13 Output; Address Bus

50 L9 VDD Power

51 L10 MA14 Output; Address Bus

52 K9 MA15 Output; Address Bus

53 L11 MA16 Output; Address Bus

54 K10 MA17 Output; Address Bus

55 J10 MA18 Output; Address Bus

56 K11 MA19 Output; Address Bus

57 J11 GND Ground

58 H10 LDS Output

59 H11 UDS Output

60 F10 NEW Output

61 G10 BOOT Output

62 G11 PCLK Output

63 G9 MR/W Output

64 F9 MD00 I/O; Data Bus

65 F11 MD01 I/O; Data Bus

Pin/Signal Assignments (Continued) CQFP PGA PIN SIGNAL NAME TYPE

66 E11 MD02 I/O; Data Bus

67 E10 MD03 I/O; Data Bus

68 E9 MD04 I/O; Data Bus

69 D11 GND Ground

70 D10 MD05 I/O; Data Bus

71 C11 MD06 I/O; Data Bus

72 B11 MD07 I/O; Data Bus

73 C10 VDD Power

74 A11 MD08 I/O; Data Bus

75 B10 MD09 I/O; Data Bus

76 B9 MD10 I/O; Data Bus

77 A10 MD11 I/O; Data Bus

78 A9 MD12 I/O; Data Bus

79 B8 MD13 I/O; Data Bus

80 A8 MD14 I/O; Data Bus

81 B6 GND Ground

82 B7 MD15 I/O; Data Bus

83 A7 GA00 Output; Address Bus

84 C7 GA01 Output; Address Bus

• C3 - Isolated Alignment Pin PGA And CQFP Pin/Signal Assignments (Continued) CQFP PGA PIN SIGNAL NAME TYPE Output Signal Descriptions SIGNAL CQFP RESET LEVEL DESCRIPTION OUTPUTS NEW 60 1 NEW: A HIGH on this pin indicates that an Instruction Fetch is in progress. BOOT 61 1 BOOT: A HIGH on this pin indicates that Boot Memory is being accessed. This pin can be set or reset by accessing bit 3 of the Configuration Register. MR/W 63 1 MEMORY READ/WRITE: A LOW on this pin indicates that a Memory Write operation is in progress. UDS 59 1 UPPER DATA SELECT: A HIGH on this pin indicates that the high byte of memory (MD15-MD08) is being accessed. LDS 58 1 LOWER DATA SELECT: A HIGH on this pin indicates that the low byte of memory (MD07-MD00) is being accessed. GIO 16 1 ASIC I/O: A LOW on this pin indicates that an ASIC Bus operation is in progress. GR/W 15 1 ASIC READ/WRITE: A LOW on this pin indicates that an ASIC Bus Write operation is in progress. PCLK 62 0 PROCESSOR CLOCK: Runs at half the frequency of ICLK. All processor cycles begin on the rising edge of PCLK. Held low extra cycles when WAIT is asserted. TCLK 2 0 TIMING CLOCK: Same frequency and phase as PCLK but continues running during Wait cycles. INTA 3 0 INTERRUPT ACKNOWLEDGE: A HIGH on this pin indicates that an Interrupt Acknowledge cycle is in progress. Input Signal, Bus, and Power Connection Descriptions SIGNAL CQFP LEAD DESCRIPTION INPUTS WAIT 13 WAIT: A HIGH on this pin causes PCLK to be held LOW and the current cycle to be extended. ICLK 14 INPUT CLOCK: Internally divided by 2 to generate all on-chip timing (CMOS input levels). RESET 12 A HIGH level on this pin resets the RTX. Must be held high for at least 4 rising edges of ICLK plus 12 ICLK cycle setup and hold times. HS-RTX2010RH

edge of PCLK. See Timing Diagrams for detail. active HIGH edge-sensitive Timer/Counter inputs. As interrupt inputs, they are sampled on the rising edge of PCLK. See Timing Diagrams for detail. processor cycle when NMI is set to Mode 0. See the Interrupt Suppression and Interrupt Controller Sections. INTSUP 5 INTERRUPT SUPPRESS: A HIGH on this pin inhibits all maskable interrupts, internal and external. GA02 1 ASIC ADDRESS: 3-bit ASIC Address Bus, which carries address information for external ASIC devices. MA19-MA14 56-51 MEMORY ADDRESS: 19-bit Memory Address Bus, which carries address information for Main Memory. GD15-GD13 17-19 ASIC DATA: 16-bit bidirectional external ASIC Data Bus, which carries data to and from off-chip I/O devices. MD15 82 MEMORY DATA: 16-bit bidirectional Memory Data Bus, which carries data to and from Main Memory. GND. This should be located as close to the RTX package as possible. Power supply ground return connections. FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT

performed simultaneously with fetching the next instruction. NOTE: contains the 5 most significant bits (20-16) of the top element of the Return Stack. FIGURE 9. HS-RTX2010RH FUNCTIONAL BLOCK DIAGRAM

data paths and simultaneous operation of some data buses. Table 3. External data is transferred by the ASIC Data Bus both of which are bidirectional. and the function being performed. Instruction Register. is also the T input to the ALU. Access section of this document. Memory (see Tables 6 thru 22 for code information). FIGURE 10. INSTRUCTION EXECUTION SEQUENCE

when the processor is reset. space required for the RESET circuit. caused by a glitch of less than four ICLK cycles duration. TABLE 1. REGISTER INITIALIZATION AND ASIC ADDRESS ASSIGNMENTS 03H 0100 0000 0000 1000 Configuration Register: Boot = 1; Interrupts Disabled; Byte Order = 0. 09H 0000 0000 0000 0000 Stack Pointer Register: The beginning address for each stack is set to a value of ‘0’. value, and is initialized to the “No Interrupt” value. 0BH 1111 1111 1111 1111 Stack Overflow Limit Register: Write-only; Each stack limit is set to its maximum value. 0DH 0000 0000 0000 0000 Data Page Register: The Data Address Page is set for page ‘0’. 0EH 0000 0000 0000 0000 User Page Register: The User Address Page is set for page ‘0’. 0FH 0000 0000 0000 0000 Code Page Register: The Code Address Page is set for page ‘0’. 11H 0000 0000 0000 0000 User Base Address Register: The User base address is set to ‘0’ within the User page. / 13H 0000 0000 0000 0000 Timer/Counter Register 0: Set to time out after 65536 clock periods or events. / 14H 0000 0000 0000 0000 Timer/Counter Register 1: Set to time out after 65536 clock periods or events. / 15H 0000 0000 0000 0000 Timer/Counter Register 2: Set to time out after 65536 clock periods or events.

each of these stacks is shown in Figure 22. Parameter Stack is 256 words deep by 16 bits wide. performing Subroutine Calls, or for storing values temporarily. portion of the Return Stack is 21 bits wide, by 256 words deep. a subroutine operation (Figure 19). identical Programmable Stack Controllers. Limit Register (see Figures 15, 16, and 17). location to be accessed in a stack push (write) operation. location to have data pushed into it is location zero. FIGURE 22. DUAL STACK ARCHITECTURE

Each 256-word stack may be subdivided into up to eight 32 word substacks, four 64 word substacks, or two 128 word substacks. This is accomplished under hardware control for simplified management of multiple tasks. Stack size is selected by writing to bits 1 and 2 of the for the Parameter Stack, and bits 9 and 10 for the Return Stack. Substacks are implemented by making bits 5-7 of the (for the Parameter Stack) and bits 13-15 of the (for the Return Stack) control bits. For example, if there were eight 32 word substacks implemented in the Parameter Stack, bits 5-7 of the are not incremented, but instead are used as an offset pointer into the Parameter Stack to indicate the beginning point (i.e., sub stack number) of each 32 word substack implemented. Because of this, a particular substack is selected by writing a value which contains both the stack pointer value and the substack number to the Each stack has a Stack Start Flag (PSF and RSF) which may be used for implementing virtual stacks. For the Parameter Stack, the Start Flag is bit zero of the , and for the Return Stack it is bit eight. If the Stack Start Flag is one, the stack starts at the bottom of the stack or substack (location 0). If the Stack Start Flag is zero, the substack starts in the middle of the stack. An exception to this occurs if the overflow limit in is set for a location below the middle of the stack. In this case, the stacks always start at the bottom locations. See Table 2 for the possible stack configurations. Manipulating the Stack Start Flag provides a mechanism for creating a virtual stack in memory which is maintained by interrupt driven handlers. Possible applications for substacks include use as a recirculating buffer (to allow quick access for a series of repeated values such as coefficients for polynomial evaluation or a digital filter), or to log a continuous stream of data until a triggering event (for analysis of data before and after the trigger without having to store all of the incoming data). The latter application could be used in a digital oscilloscope or logic analyzer. Stack Error Conditions Stack errors include overflow, underflow, and fatal errors. Overflows occur when an attempt is made to push data onto a full stack. Since the stacks wrap around, the result is that existing data on the stack will be overwritten by the new data when an overflow occurs. Underflows occur when an attempt is made to pop data off an empty stack, causing invalid data to be read from the stack. In both cases, a buffer zone may be set up by initializing and so that stack error interrupts are generated prior to an actual overflow or underflow. The limits may be determined from the contents of and using Table 2. The state of all stack errors may be determined by examining the five least significant bits of , where the stack error flags may be read but not written to. All stack error flags are cleared whenever a new value is written to . Fatal Stack Error: Each stack can also experience a fatal stack error. This error condition occurs when an attempt is made to push data onto or to pop data off of the highest location of the substack. It does not generate an interrupt (since the normal stack limits can be used to generate the interrupt). The fatal errors for the stacks are logically OR’ed together to produce bit 0 of the Interrupt Base Control Register, and they are cleared whenever is written to. The implication of a fatal error is that data on the stack may have been corrupted or that invalid data may have been read from the stack. HS-RTX2010RH Timer/Counters The HS-RTX2010RH has three 16-bit timers, each of which can be configured to perform timing or event counting. All decrement synchronously with the rising edge of TCLK. Timer registers are readable in a single machine cycle. The timer selection bits of the determine whether a timer is to be configured for external event counting or internal time-base timing. This configures the respective counter clock inputs to the on-chip TCLK signal for internal timing, or to the EI5 - EI3 input pins for external signal event counting. EI5, EI4, and EI3 are synchronized internally with TCLK. See Table 3 for Timer/Clock selection by bit values. The timers ( , and ) are all free-running, and when they time out, they reload automatically with the programmed initial value from their respective Timer Pre load Registers ( → , → , and → ), then continue timing or counting. Each timer provides an output to the Interrupt Controller to indicate when a time-out for the timer has occurred. The HS-RTX2010RH can determine the state of a timer at any time either by reading the timer’s value, or upon a time- out by using the timer’s interrupt (see the Interrupt Controller section for more information about how timer interrupts are handled). Figure 23 shows the sequence of Timer/Counter operations. SUR SPR SPR SPR SPR SUR SVR SVR SUR SVR SUR IBC SPR SPR IBC IBC TC0 TC1 TC2 TPO TC0 TP1 TC1 TP2 TC2 HS-RTX2010RH

TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS

TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS (Continued)

1. : Stack Pointer Register, : Stack Overflow Register, : Stack Underflow Register.
2. The Overflow Limit is the stack memory address at which an overflow condition will occur during a stack write operation.
3. The Underflow Limit is the stack memory address below which an underflow condition will occur during a stack read operation.
4. The Fatal Limit is the stack memory address at which a fatal error condition will occur during a stack read or write operation.
5. Stack error conditions remain in effect until a new value is written to the .
6. Stacks and sub-stacks are circular: after writing to the highest location in the stack, the next location to be written to will be the lowest location; after reading the lowest location, the highest

TABLE 2. STACK/SUBSTACK CONFIGURATIONS FOR GIVEN CONTROL BIT SETTINGS (Continued)

interrupts are the Stack Controllers and the Timer/Counters. completion of the INTA cycle. Return Stack indicating the call was caused by an interrupt. ensure that the condition that caused the interrupt is cleared. immediately upon its return. FIGURE 23. HS-RTX2010RH TIMER/COUNTER OPERATION TABLE 3. TIMER/COUNTER

to save and restore the state of the Interrupt Enable bit. appropriate bit in the Interrupt Mask Register ( ). be cleared, thereby unmasking all interrupts. completed, and a return from interrupt has been executed. must reside on Memory Page zero. compiled separately and called from the Interrupt Table. generating a new Interrupt Vector on either edge of INTA. requested, bit 09 of the will be 1. must last at least two rising and two falling edges of ICLK. TABLE 4. INTERRUPT SOURCES, PRIORITIES AND VECTORS

1 EI1 External Interrupt 1 High Level 01 0 1 1 1 0

2 PSU Parameter Stack Underflow High Level 02 0 1 1 0 1

3 RSU Return Stack Underflow High Level 03 0 1 1 0 0

4 PSV Parameter Stack Overflow High Level 04 0 1 0 1 1

5 RSV Return Stack Overflow High Level 05 0 1 0 1 0

6 EI2 External Interrupt 2 High Level 06 0 1 0 0 1

7 TCI0 Timer/Counter 0 Edge 07 0 1 0 0 0

8 TCI1 Timer/Counter 1 Edge 08 0 0 1 1 1

9 TCI2 Timer/Counter 2 Edge 09 0 0 1 1 0

10 EI3 External Interrupt 3 High Level 10 0 0 1 0 1

11 EI4 External Interrupt 4 High Level 11 0 0 1 0 0

12 EI5 External Interrupt 5 High Level 12 0 0 0 1 1

Interrupt Controller. The SWI is reset by executing an instruction that clears the flip-flop. The flip-flop is accessed by I/O Reads and Writes. Because the SWI interrupt may not be serviced immediately, the instructions which immediately follow the SWI instruction should not depend on whether or not the interrupt has been serviced, and should cause a one or two-cycle idle condition (Typically, this is done with one or two NOP instructions). If an interrupt condition occurs, but “goes away” before the processor has a chance to service it, a “No Interrupt” vector is generated. A “No Interrupt” vector is also generated if an Interrupt Acknowledge cycle takes less than two cycles to execute and no other interrupt conditions need to be serviced. To prevent unforeseen errors, it is recommended that valid code be supplied at every Interrupt Vector location, including the “No Interrupt” vector, which should always be initialized with valid code. It is recommended that Interrupt Handlers save and restore the contents of . Interrupt Suppression The HS-RTX2010RH allows maskable interrupts and Mode

1 NMIs (the NMI_MODE Flag in bit 11 of the is set) to

be suppressed, delaying them temporarily while critical operations are in progress. Critical operations are instruction sequences and hardware operations that, if interrupted, would result in the loss of data or misoperation of the hardware. (Note: Only the processor may suppress NMIs.) Standard critical operations during which interrupts are automatically suppressed by the processor include Streamed instructions (see the description of the register), Long Call sequences (see “Subroutine Calls and Returns”), and loading . In addition to this, external devices can also suppress maskable interrupts during critical operations by applying a HIGH level on the INTSUP pin for as long as required. Since the Mode 0 NMI (the NMI_MODE Flag in bit 11 of the is cleared) can cause the processor to perform an Interrupt Acknowledge Cycle in the middle of these critical operations, thereby preventing a normal return to the interrupted instruction, a Subroutine Return should be used with care from a Mode 0 NMI service routine. The Mode 0 NMI should be used only to indicate critical system errors, and the Mode 0 NMI handler should re-initialize the system. Interrupts which have occurred while interrupt suppression is in effect will be recognized on a priority basis as soon as the suppression terminates, provided the condition which generated the interrupt still exists. Stack Error Interrupts The Stack Controllers request an interrupt whenever a stack overflow or underflow condition exists. These interrupts can be cleared by rewriting . See the section on “Dual Stack Architecture” for more information regarding how the limits set into and are used. Stack Overflow:A stack overflow occurs when data is pushed onto the stack location pointed to by the , as determined in Table 5. After the processor is reset, this is location 255 in either the Parameter Stack or Return Stack. A stack overflow interrupt request stays in effect until cleared by writing a new value to the . In addition to generating an interrupt, the state of the stack overflow flags may be read out of the , bit 3 for the Parameter Stack, and bit 4 for the Return stack. See Figures 13, 15 and 16. Stack Underflow:The stack underflow limit occurs when data is popped off the stack location immediately below that pointed to by the , as determined in Table 2. The state of the stack underflow error flags may be read out of bits 1 and 2 of the for the Parameter and Return stacks respectively. In the reset state of the , an underflow will be generated at the same time that a fatal error is detected. An underflow buffer region can be set up by selecting an underflow limit greater than zero by writing the corresponding value into the . The stack underflow interrupt request stays in effect until a new value is written into the , at which time it is cleared. Timer/Counter Interrupts The timers generate edge-sensitive interrupts whenever they are decremented to 0. Because they are edge-sensitive and are cleared during an Interrupt Acknowledge cycle or during the direct reading of by software, no action is required by the handlers to clear the interrupt request. The HS-RTX2010RH ALU The HS-RTX2010RH has a 16-bit ALU capable of performing standard arithmetic and logic operations:

• ADD and SUBTRACT (A-B and B-A; with and without carry)
• AND, OR, XOR, NOR, NAND, XNOR, NOT The and registers can also undergo single bit shifts in the same cycle as a logic or arithmetic operation. In Figure 24, the control and data paths to the ALU are shown. Except for and , each of the internal core registers can be addressed explicitly, as can other internal registers in special operations such as in Step instructions. In each of these cases, the input would be addressed as a device on the ASIC Bus. When executing these instructions, the arithmetic/logic operand (a) starts out in and is placed on the T -bus. Operand (b) arrives at the ALU on the Y -bus, but can come from one of the following four sources: ; an internal register; an ASIC Bus device; or from the 5 least significant bits of . The source of operand (b) is determined by the instruction code in . The result of the ALU operation is placed into . CR CR I CR CR SPR IBC SUR SVR SPR IBC SUR IBC SUR SUR SPR IVR TOP NEXT TOP NEXT TOP NEXT IR IR TOP HS-RTX2010RH

and the Programmer’s Reference Manual for details. operation. The first step begins with containing zeros. entire process takes place in a single clock cycle.

1. The Parameter (Data) Stack and memory via
2. Memory via and an input from the ASIC Bus

5 LEAST

NOTE: Data Paths are represented by solid lines; Control Paths are represented by dashed lines. FIGURE 24. ALU OPERATIONS-CONTROL PATHS AND DATA FLOW

the contents of and remain intact. pops into and the Parameter Stack into .

1. If the most significant bit of the is set (1), the
2. If the most significant bit of the is not set (0), the

signed or unsigned bit is used. the Programmer’s Reference Manual. Parameter Stack, the and registers. FIGURE 25. HS-RTX2010RH FLOATING POINT/DSP LOGIC

word operand contained in the and registers. one clock cycle with the normalize instruction. addresses therefore map as shown in Table 5. memory data is accessed through . MA01) comes from the Program Counter Register ( ). are cleared and execution begins at page 0, word 0. and also to the Interrupt Controller section. TABLE 5. ASIC BUS MAP

address of the word in memory. See Figure 21. accesses, as well as byte swapping within 16-bit words. or odd address is being accessed (see Figures 26 and 27). FIGURE 26. MEMORY ACCESS (WORD) FIGURE 27. MEMORY ACCESS (BYTE)

Whenever a word of data is read by a Data Memory operation into the processor, it is first placed in the Register. By the time the instruction that reads that word of data is completed, however, the data may have been moved, optionally inverted, or operated on by the ALU, and placed in the Register. Whenever a Data Memory operation writes to memory, the data comes from the Register. The Byte Order Bit is bit 2 of the Configuration Register, (see Figure 11 in the “RTX Internal Registers Section). This bit is used to determine whether the default (Mode 0) or byte swap (Mode 1) method will be used in the Data Memory accesses. Word Access is designated when the bit 12 = 0 in the Memory Access Opcode, and can take one of two forms, depending upon the status of , bit 2. When bit 2 = 0, the Mode 0 method of word access is designated. Word access to an even address (A0 = 0) results in an unaltered transfer of data, as shown in Figure 26. Word access to/from an odd address (A0 = 1) while in this mode will effectively cause the Byte Order Bit to be complemented and will result in the bytes being swapped. When the bit 2 = 1, the Mode 1 method of word access is designated. Access to an even address (A0 = 0) results in a data transfer in which the bytes are swapped. Word access to an odd address (A0 = 1) while in this mode will effectively cause the Byte Order Bit to be complemented with the net result that no byte swap takes place when the data word is transferred. See Figure 26. Byte Access is designated when the bit 12 = 1 in the Memory Access Opcode, and can also take one of two forms, depending on the value of Bit 2. When the bit 2 = 0, a Byte Read from an even address in Mode 0 causes the upper byte (MD15-MD08) of memory data to be read into the lower byte position (MD07-MD00) of , while the upper byte (MD15-MD08) is set to 0. A Byte Write operation accessing an even address will cause the byte to be written from the lower byte position (MD07-MD00) of into the upper byte position (MD15-MD08) of memory. The data in the lower byte position (MD07-MD00) in memory will be left unaltered. Accessing an odd address for either of these operations will cause the Byte Order Bit to be complemented, with the net result that no swap will occur. See Figure 27. When bit 2 = 1, the Mode 1 method of memory access is used. Accessing an even address in this mode means that a Byte Read operation will cause the lower byte of data to be transferred without a swap operation. A Byte Write in this mode will also result in an unaltered byte transfer. Conversely, accessing an odd address for a byte operation while in Mode 1 will cause the Byte Order Bit to be complemented. In a Byte Read operation, this will result in the upper byte (MD15-MD08) of data being swapped into the lower byte position (MD07-MD00), while the upper byte is set to 0 (MD15-MD08 set to 0). See Figure 27. A Byte Write operation accessing an odd address will cause the byte to be swapped from the lower byte position (MD07-MD00) of the processor register into the upper byte position (MD15-MD08) of the Memory location. The data in the lower byte position (MD07-MD00) in that Memory location will be left unaffected. NOTE: These features are for Main Memory data access only, and have no effect on instruction fetches, long literals, or User Data Memory. Subroutine Calls And Returns The RTX can perform both “short” subroutine calls and “long” subroutine calls. A short subroutine call is one for which the subroutine code is located within the same Code page as the Call instruction, and no processor cycle time is expended in reloading the . Performing a long subroutine call involves transferring execution to a different Code page. This requires that the be loaded with the new Code page as described in the Memory Access Section, followed immediately by the Subroutine Call instruction. This adds two additional cycles to the execution time for the Subroutine Call. For all instructions except Subroutine Calls or Branch instructions, bit 5 of the instruction code represents the Subroutine Return Bit. If this bit is set to 1, a Return is performed whereby the return address is popped from the Return Stack, as indicated in Figure 19. The page for the return address comes from the . The contents of the Register are written to the , and the contents of the are written to the so that execution resumes at the point following the Subroutine Call. The Return Stack is also popped at this time. HS-RTX2010RH Software The HS-RTX2010RH is designed around the same architecture as the RTX 2000, and is a hardware implementation of the Virtual Forth Engine. As such, it does not require the additional assembly or machine language software development typical of most real-time microcontrollers. The instruction set for the HS-RTX2010RH TForth compiler combines multiple high level instructions into single machine instructions without having to rely on either pipelines or caches. This optimization yields an effective throughput which is faster than the processor’s clock speed, while avoiding the unpredictable execution behavior exhibited by most RISC processors caused by pipeline flushes and cache misses.

2010 Compilers

Intersil offers a complete ANSI C cross development environment for the HS-RTX2010RH. The environment provides a powerful, user-friendly set of software tools NEXT TOP NEXT CR IR CR CR CR IR CR CR NEXT NEXT CR CPR CPR IPR I PC IPR CPR HS-RTX2010RH

assembler, linker, profiler, and PROM programmer interface. following sections for instruction set information. TABLE 6. INSTRUCTION SET SUMMARY m-read Read data (byte or word) from memory location addressed by contents of Register into Register. m-write Write contents (byte or word) of Register into memory location addressed by contents of Register. chip peripheral registers can be done with a g-read command. peripheral registers can be done with a g-write command. u-read Read contents (word only) of User Space location (address field uuuuu of instruction) into Register. u-write Write contents (word only) of Register into User Space location (address field uuuuu of instruction). SWAP Exchange contents of and registers. DUP Copy contents of Register to Register, pushing previous contents of onto Stack Memory. original contents of Register to Stack Memory. and the original contents of the top Stack Memory location in . inv Perform 1’s complement on contents of Register, if i bit in instruction is 1. alu-op Perform appropriate cccc or aaa ALU operation from Table 20 on contents of and registers. are pushed into , and the original contents of are pushed onto Stack Memory. R Perform a Return From Subroutine if bit = 1. NOTE: All unused opcodes are reserved for future architectural enhancements. TABLE 7. INSTRUCTION REGISTER BIT FIELDS (BY FUNCTION)

TABLE 8. HS-RTX2010RH AND ACCESS OPERATIONS (Note) NOTE: See the RTX Programmer’s Reference Manual for a complete listing of typical software functions. TABLE 9. HS-RTX2010RH RESERVED I/O OPCODES TABLE 10. SUBROUTINE CALL INSTRUCTIONS

TABLE 11. SUBROUTINE RETURN (as implied here by hyphens). TABLE 12. BRANCH INSTRUCTIONS NOTE: See the Programmer’s Reference Manual for further information regarding the branch address field. TABLE 13. REGISTER AND I/O ACCESS INSTRUCTIONS TABLE 14. SHORT LITERAL INSTRUCTIONS

TABLE 15. LONG LITERAL INSTRUCTIONS TABLE 16. MEMORY ACCESS INSTRUCTIONS

TABLE 17. USER SPACE INSTRUCTIONS TABLE 18. ALU FUNCTION INSTRUCTIONS TABLE 19. STEP MATH FUNCTIONS (NOTE 25)

1. These instructions perform multi-step math functions such as multiplication, division and square root functions. Use of either the Streamed

instruction mode or masking of interrupts is recommended to avoid erroneous results when performing Step Math operations.

TABLE 20. ALU LOGIC FUNCTIONS/OPCODES

0011 NOR

0101 SWAP-c With Borrow

0111 NAND

1011 XNOR

TABLE 21. SHIFT FUNCTIONS

0000 No Shift CY Z15 Zn Z0 TN15 TNn TN0

0110 U2/ Logical Right Shift 0 0 Zn+1 Z1 TN15 TNn TN0

1000 N2* Left Shift of CY Z15 Zn Z0 TN14 TNn-1 0

1001 N2*c Rotate Left CY Z15 Zn Z0 TN14 TNn-1 CY

1010 D2* 32-Bit Left Shift Z15 Z14 Zn-1 TN15 TN14 TNn-1 0

1011 D2*c 32-Bit Rotate Left Z15 Z14 Zn-1 TN15 TN14 TNn-1 CY

1110 UD2/ 32-Bit Logical Right Shift 0 0 Zn+1 Z1 Z0 TNn+1 TN1

1111 D2/ 32-Bit Right Shift Z15 Z15 Zn+1 Z1 Z0 TNn+1 TN1

NOTE: See the Programmer’s Reference Manual.

TABLE 22. MAC/BARREL SHIFTER/LZD INSTRUCTIONS

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Die Characteristics DIE DIMENSIONS: 364 mils x 371 mils x 21 mils±1mil INTERFACE MATERIALS: Glassivation: Type: SiO2 Thickness: 8kÅ ±1kÅ Top Metallization: Type: Al/Si/Cu Thickness: 7.5kÅ ±2kÅ Substrate: TSOS5 CMOS, Silicon on Sapphire Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (SOS) ADDITIONAL INFORMATION: Worst Case Current Density: 1.0 x 105 A/cm2 Metallization Mask Layout HS-RTX2010RH MA16 (53) MA15 (52) MA14 (51) VCC (50) MA13 (49) MA12 (48) MA11 (47) MA10 (46) MA09 (45) GND (44) MA08 (43) MA07 (42) MA06 (41) MA05 (40) MA04 (39) MA03 (38) MA02 (37) MA01 (36) GD00 (35) GD01 (34) GD02 (33) GND (32) GD03 (31) GD04 (30) GD05 (29) GD06 (28) VCC (27) GD07 (26) GD08 (25) GD09 (24) GD10 (23) GD11 (22) GD12 (21) GND (20) GD13 (19) GD14 (18) GD15 (17) GIO (16) GR/W (15) ICLK (14) WAIT (13) RESET (12) (11) EI5 (10) EI4 (9) EI3 (8) EI2 (7) EI1 (6) VCC (5) INTSUP (4) NMI (3) INTA (2) TCLK (CQFP PIN 1) GA02 (84) GA01 (83) GA00 (82) MD15 (81) GND (80) MD14 (79) MD13 (78) MD12 (77) MD11 (76) MD10 (75) MD09 (74) MD08 (73) VCC (72) MD07 (71) MD06 (70) MD05 (69) GND (68) MD04 (67) MD03 (66) MD02 (65) MD01 (64) MD00 (63) MR/W (62) PCLK (61) BOOT (60) NEW (59) UDS (58) LDS (57) GND (56) MA19 (55) MA18 (54) MA17 HS-RTX2010RH