HS-565BRH INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically Screened to SMD # 5962-96755
  • QML Qualified per MIL-PRF-38535 Requirements
  • DAC and Reference on a Single Chip
  • Pin Compatible with AD-565A and HI-565A
  • Very High Speed: Settles to 0.50 LSB in 500ns Max
  • Monotonicity Guaranteed Over Temperature
  • 0.50 LSB Max Nonlinearity Guaranteed Over Temperature
  • Low Gain Drift oC
  • ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at 25oC)

Applications

  • High Speed A/D Converters
  • Precision Instrumentation
  • Signal Reconstruction Functional Diagram

Ordering Information

MKT. NUMBER TEMP. RANGE (oC) 5962R9675502V9A HS0-565BRH-Q 25 5962R9675502VJC HS1-565BRH-Q -55 to 125 5962R9675502VXC HS9-565BRH-Q -55 to 125 HS9-565BRH/PROTO HS9-565BRH/PROTO -55 to 125 REF OUT VCC 19.95K REF 10V 5REF 3.5K IREF 0.5mA -VEE PWR GND 71 2 24 . . . 13 MSB LSB (4X IREF X CODE)GND IN 20V SPAN 10V SPAN OUTIO DAC 9.95K BIP. OFF. 2.5K Data Sheet January 2003 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

(SBDIP) TOP VIEW HS9-565BRH MIL-STD-1835 CDFP4-F24 (CERAMIC FLATPACK) TOP VIEW NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND BIT 1 IN (MSB) BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 8 IN BIT 10 IN BIT 11 IN BIT 12 IN (LSB) BIT 2 IN BIT 7 IN BIT 9 IN NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND BIT 1 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 8 IN BIT 10 IN BIT 11 IN BIT 12 IN BIT 2 IN BIT 7 IN BIT 9 IN (LSB) (MSB) HS-565BRH

NOTES: D1 = D2 = D3 = IN4002 or Equivalent F0 to F11: VIH = 5.0V ±0.5V VIL = 0.0V ±0.5V F0 = 100kHz ±10% (50% Duty Cycle) F1 = F0/2 F7 = F0/128 F2 = F0/4 F8 = F0/256 F3 = F0/8 F9 = F0/512 F4 = F0/16 F10 = F0/1024 F5 = F0/32 F11 = F0/2048 F6 = F0/64 Radiation Bias Circuit NOTE: Power Supply Levels are ±0.5V Definitions of Specifications Digital Inputs The HS-565BRH accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two’s Complement (see note below), or Offset Binary, (See Operating Instructions). Accuracy Nonlinearity - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON). Differential Nonlinearity - For a D/A converter, it is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. Settling Time Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within 0.50 LSB of final value. Drift Gain Drift - The change in full scale analog output over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Gain error is measured with respect to 25oC at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH - oC) and low ranges (25oC - TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst case drift. Offset Drift - The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full scale range per oC (ppm of FSR/oC). Offset error is measured with respect to 25oC at high (TH) and low (TL) temperatures. Offset drift is calculated for both high (TH - 25 oC) and low (25oC - TL) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst case drift. C3D3 +10V NC C1D1 +15V C2D2 -15V F10 F11 NC VCC REF GND REF OUT REF IN -VEE BIP OFF OUT 10V SPAN 20V SPAN PWR GND BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 +15V NC NC VCC REF GND REF OUT REF IN -VEE BIP OFF OUT 10V SPAN 20V SPAN PWR GND BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 -15V +10V +5V DIGITAL INPUT ANALOG OUTPUT STRAIGHT BINARY OFFSET BINARY (NOTE) TWO’S COMPLEMENTMSB...LSB 000.... 000 Zero -FS (Full Scale) Zero 111.... 111 +FS - 1LSB +FS - 1LSB Zero - 1LSB FS - 1LSB Zero - 1LSB +FS - 1LSB NOTE: Invert MSB with external inverter to obtain Two’s Complement Coding HS-565BRH

settling time as a basis for design. be a reliable and repeatable way to measure settling time. entry within a window of ±0.50 LSB about the settled value. for the measurement of case (d).

  • Adjust the delay on generator number 2 for a tX of several microseconds. This assures that the DAC output has settled to its final wave.
  • Switch on the LSB (+5V)
  • Adjust the VLSB supply for 50% triggering at COMPARATOR OUT. This is indicated by traces of equal brightness on the oscilloscope display as shown in Figure 3B. Note DVM reading.
  • Switch to LSB to Pulse (P)
  • Readjust the VLSB supply for 50% triggering as before, and note DVM reading. One LSB equals one tenth the difference in the DVM readings noted above.
  • Adjust the VLSB supply to reduce the DVM reading by 5 LSBs (DVM reads 10X, so this sets the comparator to sense the final settled value minus 0.50 LSB). Comparator output disappears.
  • Reduce generator number 2 delay until comparator output reappears, and adjust for “equal brightness”.
  • Measure tX from scope as shown in Figure 3B. Settling time equals tX + tD, i.e. tX + 15ns. (a) tON, to final value +0.50 LSB (b) tON, to final value -0.50 LSB (c) tOFF, to final value +0.50 LSB (d) OFF, to final value -0.50 LSB

TABLE 1. OPERATING MODES AND CALIBRATION

The HS-565BRH has two ground terminals, pin 5 (REF GND) and pin 12 (PWR GND). These should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (If such a point exists, then separate paths are required to pins 5 and 12). The current through pin 5 is near zero DC (Note); but pin 12 carries up to 1.75mA of code - dependent current from bits 1, 2, and 3. The general rule is to connect pin 5 directly to the system “quiet” point, usually called signal or analog ground. Connect pin 12 to the local digital or power ground. Then, of course, a single path must connect the analog/signal and digital/power grounds. NOTE: Current cancellation is a two step process within the HS-565BRH in which code dependent variations are eliminated, the resulting DC current is supplied internally. First an auxiliary 9-bit R-2R ladder is driven by the complement of the DACs input code. Together, the main and auxiliary ladders draw a continuous 2.25mA from the internal ground node, regardless of input code. Part of the DC current is supplied by the zener voltage reference, and the remainder is sourced from the pos itive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). Layout Connections to pin 9 (IOUT) on the HS-565BRH are most critical for high speed performance. Output capacitance of the DAC is only 20pF, so a small change of additional capacitance may alter the op amp’s stability and affect settling time. Connections to pin 9 should be short and few. Component leads should be short on the side connecting to pin 9 (as for feedback capacitor C). See the Settling Time section. Bypass Capacitors Power supply bypass capacitors on the op amp will serve the HS-565BRH also. If no op amp is used, a 0.01µF ceramic capacitor from each supply terminal to pin 12 is sufficient, since supply current variations are small. FIGURE 3A. . FIGURE 3B. VLSB SUPPLY0.1µFDVM COMPARATOR OUT B C 90 200K NC 2.5K 20V ± 20% BIAS TURN ON TURN OFF 9.95K 2mA HS-565BRH D PULSE GENERATOR NO. 2 OUT P PULSE GENERATOR NO. 1 SYNC IN TRIG OUT OUT A ~100 kHz STROBE IN LSB 50% DIGITAL INPUT DAC OUTPUT COMP. STROBE COMP. OUT “EQUAL BRIGHTNESS” +3V -400mV 0.8V (TURN OFF) A B C D 50% tX tD = COMPARATOR DELAY SETTLING TIME -0.50LSB HS-565BRH

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com Die Characteristics DIE DIMENSIONS: 179 mils x 107 mils x 19 mils INTERFACE MATERIALS: Glassivation: Type: AlCu Thickness: 8kÅ ±1kÅ Top Metallization: Type: Al/Copper Thickness: 16kÅ ±2kÅ Substrate: Bipolar DI, Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: Tie Substrate to VREF GND ADDITIONAL INFORMATION: Worst Case Current Density: 2.0 x 105 A/cm2 Transistor Count: 200 Metallization Mask Layout HS-565BRH VCC (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11BIT 12 (LSB) POWER GND 20V SPAN 10V SPAN IDAC OUT BIPOLAR -VS VREF IN VREF GND VREF OUT NC NC 1 A HS-565BRH