HS0-565BEH-Q

HS-565BRH_12 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 9

Technical content

Features

• Electrically Screened to SMD # 5962-96755
• QML Qualified per MIL-PRF-38535 Requirements
• DAC and Reference on a Single Chip
• Pin Compatible with AD-565A and HI-565A
• Very High Speed: Settles to 0.50 LSB in 500ns Max
• Monotonicity Guaranteed Over Temperature
• 0.50 LSB Max Nonlinearity Gu aranteed Over Temperature
• L o w G a i n D r i f t
• ±0.75 LSB Accuracy Guaranteed Over Temperature (±0.125 LSB Typical at +25°C)

Applications

• H i g h S p e e d A / D C o n v e r t e r s
• Precision Instrumentation
• Signal Reconstruction

FIGURE 1. FUNCTIONAL DIAGRAM CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners.

HS-565BRH, HS-565BEH 2 FN4607.4 May 7, 2012 Pin Configurations HS1-565BRH, HS1-565BEH MIL-STD-1835 CDIP2-T24 (SBDIP) TOP VIEW HS9-565BRH, HS9-565BEH MIL-STD-1835 CDFP4-F24 (CERAMIC FLATPACK) TOP VIEW NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND BIT 1 IN (MSB) BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 8 IN BIT 10 IN BIT 11 IN BIT 12 IN (LSB) BIT 2 IN BIT 7 IN BIT 9 IN NC NC VCC REF OUT REF GND REF IN -VEE BIPOLAR RIN IDAC OUT 10V SPAN 20V SPAN PWR GND BIT 1 IN BIT 3 IN BIT 4 IN BIT 5 IN BIT 6 IN BIT 8 IN BIT 10 IN BIT 11 IN BIT 12 IN BIT 2 IN BIT 7 IN BIT 9 IN (LSB) (MSB)

Ordering Information

ORDERING NUMBER PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # 5962R9675502V9A HS0-565BRH-Q +25 5962R9675502VJC HS1-565BRH-Q Q 5962R96 75502VJC -55 to +125 24 Ld SBDIP D24.6 5962R9675502VXC HS9-565BRH-Q Q 5962R96 75502VXC -55 to +125 24 Ld Flatpack K24.A HS9-565BRH/PROTO HS9-565BRH/PROTO HS9- 565BRH /PROTO -55 to +125 5962R9675503V9A HS0-565BEH-Q +25 5962R9675503VJC HS1-565BEH-Q Q 5962R96 75503VJC -55 to +125 24 Ld SBDIP D24.6 5962R9675503VXC HS9-565BEH-Q Q 5962R96 75503VXC -55 to +125 24 Ld Flatpack K24.A NOTE: These Intersil Pb-free Hermetic packag ed products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

HS-565BRH, HS-565BEH 3 FN4607.4 May 7, 2012 Burn-In Bias Circuit NOTES: D1 = D2 = D3 = IN4002 or Equivalent F0 to F11: VIH = 5.0V ±0.5V VIL = 0.0V ±0.5V F0 = 100kHz ±10% (50% Duty Cycle) F1 = F0/2 F7 = F0/128 F2 = F0/4 F8 = F0/256 F3 = F0/8 F9 = F0/512 F4 = F0/16 F10 = F0/1024 F5 = F0/32 F11 = F0/2048 F6 = F0/64 Radiation Bias Circuit NOTE: Power Supply Levels are ±0.5V Definitions of Specifications Digital Inputs The HS-565BRH, HS-565BEH accepts digital input codes in binary format and may be user connected for any one of three binary codes. Straight binary, Two’s Complement (see note below), or Offset Binary. Accuracy Nonlinearity - Nonlinearity of a D/A converter is an important measure of its accuracy. It describes the deviation from an ideal straight line transfer curve drawn between zero (all bits OFF) and full scale (all bits ON). Differential Nonlinearity - For a D/A converter, it is the difference between the actual output voltage change and the ideal (1 LSB) voltage change for a one bit change in code. A Differential Nonlinearity of ±1 LSB or less guarantees monotonicity; i.e., the output always increases and never decreases for an increasing input. Settling Time Settling time is the time required for the output to settle to within the specified error band for any input code transition. It is usually specified for a full scale or major carry transition, settling to within 0.50 LSB of final value. Drift Gain Drift - The change in full scale analog output over the specified temperature range expressed in parts per million of full scale range per °C (ppm of FSR/°C). Gain error is measured with respect to +25°C at high (TH) and low (TL) temperatures. Gain drift is calculated for both high (TH - +25°C) and low ranges (+25°C - TL) by dividing the gain error by the respective change in temperature. The specification is the larger of the two representing worst case drift. Offset Drift - The change in analog output with all bits OFF over the specified temperature range expressed in parts per million of full scale range per °C (ppm of FSR/°C). Offset error is measured with respect to +25°C at high (TH) and low (TL) temperatures. Offset drift is calculated for both high (TH - +25°C) and low (+25°C - TL) ranges by dividing the offset error by the respective change in temperature. The specification given is the larger of the two, representing worst case drift. C3D3 +10V NC C1D1 +15V C2D2 -15V F10 F11 NC VCC REF GND REF OUT REF IN -VEE BIP OFF OUT 10V SPAN 20V SPAN PWR GND BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 +15V NC NC VCC REF GND REF OUT REF IN -VEE BIP OFF OUT 10V SPAN 20V SPAN PWR GND BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11 BIT 12 -15V +10V +5V DIGITAL INPUT ANALOG OUTPUT STRAIGHT BINARY OFFSET BINARY TWO’S COMPLEMENT (Note)MSB...LSB 000.... 000 Zero -FS (Full Scale) Zero FS Zero -FS 111.... 111 +FS - 1LSB +FS - 1LSB Zero - 1LSB NOTE: Invert MSB with external inverter to obtain Two’s Complement Coding

settling time as a basis for design. application - use in a successive approximation A/D converter. repeatable way to measure settling time. the measurement of case (d).

• Adjust the delay on generator number 2 for a tX of several microseconds. This assures that the DAC output has settled to its final wave.
• Switch on the LSB (+5V)
• Adjust the VLSB supply for 50% triggering at COMPARATOR OUT. This is indicated by traces of equal brightness on the oscilloscope display as shown in Figure 4B. Note DVM reading.
• S w i t c h t o L S B t o P u l s e ( P )
• Readjust the VLSB supply for 50% triggering as before, and note DVM reading. One LSB equals one tenth the difference in the DVM readings noted above.
• Adjust the VLSB supply to reduce the DVM reading by 5 LSBs (DVM reads 10X, so this sets the comparator to sense the final settled value minus 0.50 LSB). Comparator output disappears.
• Reduce generator number 2 delay until comparator output reappears, and adjust for “equal brightness”.
• Measure tX from scope as show n in Figure 4B. Settling time equals tX + tD, i.e., tX + 15ns. (a) tON, to final value +0.50 LSB (b) tON, to final value -0.50 LSB (c) tOFF, to final value +0.50 LSB (d) OFF, to final value -0.50 LSB

TABLE 1. OPERATING MODES AND CALIBRATION

HS-565BRH, HS-565BEH 6 FN4607.4 May 7, 2012 Other Considerations Grounds The HS-565BRH, HS-565BEH has two ground terminals, pin 5 (REF GND) and pin 12 (PWR GND). These should not be tied together near the package unless that point is also the system signal ground to which all returns are connected. (If such a point exists, then separate paths are required to pins 5 and 12). The current through pin 5 is near zero DC (Note); but pin 12 carries up to 1.75mA of code - dependent current from bits 1, 2, and 3. The general rule is to connect pin 5 directly to the system “quiet” point, usually called signal or analog ground. Connect pin 12 to the local digital or power ground. Then, of course, a single path must connect the analog/signal and digital/power grounds. NOTE: Current cancellation is a two step process within the HS-565BRH, HS-565BEH in which code dependent variations are eliminated, the resulting DC current is supplied internally. First an auxiliary 9-bit R-2R ladde r is driven by the complement of the DACs input code. Together, the main and auxiliary ladders draw a continuous 2.25mA from the internal ground node, regardless of input code. Part of the DC current is supplied by the zener voltage reference, and the remainder is sourced from the positive supply via a current mirror which is laser trimmed for zero current through the external terminal (pin 5). Layout Connections to pin 9 (IOUT) on the HS-565BRH, HS-565BEH are most critical for high speed performance. Output capacitance of the DAC is only 20pF, so a small change of additional capacitance may alter the op amp’s stability and affect settling time. Connections to pin 9 should be short and few. Component leads should be short on the side connecting to pin 9 (as for feedback capacitor C). See the “Settling Time” section on page 5. Bypass Capacitors Power supply bypass capacitors on the op amp will serve the HS-565BRH, HS-565BEH also. If no op amp is used, a 0.01µF ceramic capacitor from each supply terminal to pin 12 is sufficient, since supply current variations are small. FIGURE 4A. FIGURE 4B. VLSB SUPPLY0.1µFDVM COMPARATOR OUT B C 90 200k NC 2.5k 20V ± 20% BIAS TURN ON TURN OFF 9.95k 2mA HS-565BRH D PULSE GENERATOR NO. 2 OUT P PULSE GENERATOR NO. 1 SYNC IN TRIG OUT OUT A ~100 kHz STROBE IN LSB 50% DIGITAL INPUT DAC OUTPUT COMP. STROBE COMP. OUT “EQUAL BRIGHTNESS” +3V -400mV 0.8V (TURN OFF) A B C D 50% tX tD = COMPARATOR DELAY SETTLING TIME -0.50LSB

HS-565BRH, HS-565BEH 7 FN4607.4 May 7, 2012 Die Characteristics DIE DIMENSIONS: 179 mils x 107 mils x 19 mils INTERFACE MATERIALS: Glassivation: Type: AlCu Thickness: 8kÅ ±1kÅ Top Metallization: Type: Al/Copper Thickness: 16kÅ ±2kÅ Substrate: Bipolar DI, Backside Finish: Silicon ASSEMBLY RELATED INFORMATION Substrate Potential: Tie Substrate to VREF GND ADDITIONAL INFORMATION: Worst Case Current Density: 2.0 x 105 A/cm2 Transistor Count: 200 Metallization Mask Layout HS-565BRH, HS-565BEH VCC (MSB) BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 BIT 9 BIT 10 BIT 11BIT 12 (LSB) POWER GND 20V SPAN 10V SPAN IDAC OUT BIPOLAR -VS VREF IN VREF GND VREF OUT NC NC 1 A

HS-565BRH, HS-565BEH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4607.4 May 7, 2012 For additional products, see www.intersil.com/product_tree Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identi- fication mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D24.6 MIL-STD-1835 CDIP2-T24 (D-3, CONFIGURATION C)

24 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.225 - 5.72 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.500 0.610 12.70 15.49 - e 0.100 BSC 2.54 BSC - eA 0.600 BSC 15.24 BSC - eA/2 0.300 BSC 7.62 BSC - L 0.120 0.200 3.05 5.08 - Q 0.015 0.075 0.38 1.91 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N2 4 2 4 8 Rev. 0 4/94

HS-565BRH, HS-565BEH 9 FN4607.4 May 7, 2012 Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be located ad- jacent to pin one and shall be locat ed within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identi- fication mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M ap- plies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be m easured at the centroid of the fin- ished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the menis- cus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and toleranci ng per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K24.A MIL-STD-1835 CDFP4-F24 (F-6A, CONFIGURATION B)

24 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.640 - 16.26 3 E 0.350 0.420 9.14 10.67 - E1 - 0.450 - 11.43 3 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.250 0.370 6.35 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 N2 4 2 4- Rev. 0 5/18/94