HS-4424RH_14 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Electrically screened to DESC SMD # 5962-99560
  • QML qualified per MIL-PRF-38535 requirements
  • EH version acceptance tested to 50krad(Si) (LDR)
  • R a d i a t i o n e n v i r o n m e n t - Latch-up immune - Low dose rate immune
  • Low voltage lock-out feature
  • Consistent delay times with V CC changes
  • L o w p o w e r c o n s u m p t i o n - 40mW with inputs high - 20mW with inputs low

Applications

  • Switching power supplies
  • D C / D C c o n v e r t e r s
  • M o t o r c o n t r o l l e r s Pin Configuration HS-4424RH, HS-4424EH, HS-4424BRH, HS-4424BEH (FLATPACK CDFP4-F16) TOP VIEW NC IN A NC GND A GND B NC IN B NC 11 6 NC OUT A OUT A V CC VCC OUT B OUT B NC NOTE: Pins 4 and 5, 10 and 11, 12 and 13, 14 and 15 are double-bonded to their same electrical points on the die. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 1999, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. September 24, 2013 FN4739.2

HS-4424RH, HS-4424EH, HS-4424BRH, HS-4424BEH 2 FN4739.2 September 24, 2013

Ordering Information

(Note 2) PART NUMBER (Note 1) TEMPERATURE RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # 5962F9956004V9A HS0-4424BEH-Q -55 to +125 DIE 5962F9956002V9A HS0-4424BRH-Q -55 to +125 DIE HS0-4424BRH/SAMPLE HS0-4424BRH/SAMPLE -55 to +125 DIE SAMPLE 5962F9956003V9A HS0-4424EH-Q -55 to +125 DIE 5962F9956001V9A HS0-4424RH-Q -55 to +125 DIE HS0-4424RH/SAMPLE HS0-4424RH/SAMPLE -55 to +125 DIE SAMPLE 5962F9956001VXC HS9-4424RH-Q -55 to +125 16 Ld Flatpack K16.A 5962F9956004VXC HS9-4424BEH-Q -55 to +125 16 Ld Flatpack K16.A 5962F9956003VXC HS9-4424EH-Q -55 to +125 16 Ld Flatpack K16.A 5962F9956002QXC HS9-4424BRH-8 -55 to +125 16 Ld Flatpack K16.A 5962F9956002VXC HS9-4424BRH-Q -55 to +125 16 Ld Flatpack K16.A HS9-4424BRH/PROTO HS9-4424BRH/PROTO -55 to +125 16 Ld Flatpack K16.A HS9-4424RH/PROTO HS9-4424RH/PROTO -55 to +125 16 Ld Flatpack K16.A 5962F9956001QXC HS9-4424RH-8 -55 to +125 16 Ld Flatpack K16.A NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table on page 2 must be used when ordering..

HS-4424RH, HS-4424EH, HS-4424BRH, HS-4424BEH Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4739.2 September 24, 2013 For additional products, see www.intersil.com/en/products.html Die Characteristics DIE DIMENSIONS: 4890μm x 3370μm (193 mils x 133 mils) Thickness: 483μm ± 25.4μm (19 mils ± 1 mil) INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ± 1.0kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ± 2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 125 Metallization Mask Layout HS-4424RH, HS-4424EH, HS-4424BRH, HS-4424BEH GND (5) IN B (7) OUT B (10) OUT B (11) VCC (12) VCC (13) GND (4) IN A (2) OUT A (15) OUT A (14)