HS0-303CEH

HS-303CEH INTERSIL | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 10

Technical content

2 FN8399.1 April 19, 2013 Pin Configuration HS-303CEH (14 LD FLATPACK) TOP VIEW NC GND IN1 IN2 Pin Descriptions PIN NUMBER PIN NAME PIN DESCRIPTION

1 NC Not Electrically Connected

2 S3 Analog Switch: Source connection

3 D3 Analog Switch: Drain Connection

4 D1 Analog Switch: Drain Connection

5 S1 Analog Switch: Source connection

6 IN1 Digital Control Input for SW1 and SW3

8 V- Negative Power Supply

9 IN2 Digital Control Input for SW2 and SW4

10 S2 Analog Switch: Source connection

11 D2 Analog Switch: Drain Connection

12 D4 Analog Switch: Drain Connection

13 S4 Analog Switch: Source connection

14 V+ Positive Power Supply

Ordering Information

TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # 5962R9581308VXC HS9-303CEH-Q -55 to +125 14 Ld Flatpack K14.A 5962R9581308V9A HS0-303CEH-Q -55 to +125 Die N/A HS9-303CEH/PROTO HS9-303CEH/PROTO -55 to +125 14 Ld Flatpack K14.A HS0-303CEH/SAMPLE HS0-303CEH/SAMPLE -55 to +125 Die N/A NOTE: These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.

3 FN8399.1 April 19, 2013 Absolute Maximum Ratings Thermal Information Analog Input Voltage Digital Input Voltage Peak Current (S or D) Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) Package Power Dissipation at 125°C http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For θJC, the “case temp” location is the center of the package underside. Electrical Specifications VSUPPLY = ±15V unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS +rDS(ON) “Switch On” Resistance V D = 10V, IS = -10mA 35 75 Ω -rDS(ON) “Switch On” Resistance V D = -10V, IS = 10mA 35 75 Ω +IS(OFF) Leakage Current into Source of an “OFF” Switch V S = +14V, VD = -14V -150 0.05 150 nA VS = +15V, VD = -15V -20 20 µA -IS(OFF) Leakage Current into Source of an “OFF” Switch V S = -14V, VD = +14V -150 0.5 150 nA VS = -15V, VD = +15V -20 20 µA +ID(OFF) Leakage Current into Drain of an “OFF” Switch V S = +14V, VD = -14V -150 0.05 150 nA VS = +15V, VD = -15V -20 20 µA -ID(OFF) Leakage Current into Drain of an “OFF” Switch V S = -14V, VD = +14V -150 0.5 150 nA VS = -15V, VD = +15V -20 20 µA +ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) VS = +14V, VD = +14V -100 -0.1 100 nA -ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) VS = -14V, VD = -14V -100 0.01 100 nA IAL Low Level Input Address Current All Channels V A = 0.8V -1000 0.03 1000 nA IAH High Level Input Address Current All Channels V A = 4.0V -1000 0.03 1000 nA I+ Positive Supply Current All Channels V A = 0.8V 45 150 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V 0.15 0.6 mA I- Negative Supply Current All Channels V A = 0.8V -0.1 -100 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V -0.1 -100 µA CIS(OFF) Switch Input Capacitance F rom Source to GND (Notes 3, 4) 28 pF CC1 Driver Input Capacitance V A = 0V (Notes 3, 4) 10 pF

4 FN8399.1 April 19, 2013 CC2 Driver Input Capacitance V A = 15V (Notes 3, 4) 10 pF COS Switch Output Measured Drain to GND (Notes 3, 4) 28 pF VISO Off Isolation V GEN = 1Vp-p, f = 1MHz (Notes 3, 4) 40 dB VCR Cross Talk V GEN = 1Vp-p, f = 1MHz (Notes 3, 4) 40 dB VCTE Charge Transfer Error V S = GND, CL= 0.01µF (Notes 3, 4) 15 mV tOPEN Break-Before-Make Time Delay R L = 300Ω, VS = 3V, VAH = 5V, VAL = 0V 10 50 300 ns tON Switch Turn “ON” Time R L = 300Ω, VS = 3V, VAH = 4V, VAL = 0V 250 500 ns tOFF Switch Turn “OFF” Time R L = 300Ω, VS = 3V, VAH = 4V, VAL = 0V 200 450 ns NOTES: 3. Limits established by characteriza tion and are not production tested. 4. VAL = 0V and VAH = 4V. 5. Parameters with MIN and/or MAX limits are 100% tested at +25° C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Post Radiation Characteristics VSUPPLY = ±15V unless otherwise specified. This data is typical test data post radiation exposure at a rate of 50 to 300rad(Si)/s. This data is intended to show typical parameter shifts due to total ionizing dose (high dose radiation) TA= +25°C. SYMBOL PARAMETER TEST CONDITIONS 0k 100k UNITS +rDS(ON) “Switch On” Resistance V D = 10V, IS = -10mA 34 35 Ω -rDS(ON) “Switch On” Resistance V D = -10V, IS = 10mA 28 29 Ω +IS(OFF) Leakage Current into Source of an “OFF” Switch V S = +14V, VD = -14V -0.20 -0.31 nA VS = +15V, VD = -15V -0.003 -0.47 µA -IS(OFF) Leakage Current into Source of an “OFF” Switch V S = -14V, VD = +14V 0.30 0.84 nA VS = -15V, VD = +15V 0.001 0.02 µA +ID(OFF) Leakage Current into Drain of an “OFF” Switch V S = +14V, VD = -14V -1.20 -0.90 nA VS = +15V, VD = -15V -0.001 -0.001 µA -ID(OFF) Leakage Current into Drain of an “OFF” Switch V S = -14V, VD = +14V 0.31 0.90 nA VS = -15V, VD = +15V 0.0003 0.001 µA +ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) -ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) VS = -14V, VD = -14V 0.15 0.28 nA IAL Low Level Input Address Current All Channels V A = 0.8V 0.35 0.25 nA IAH High Level Input Address Current All Channels V A = 4.0V 1.98 1.47 nA I+ Positive Supply Current All Channels V A = 0.8V 55 53 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V 167.2 113.7 µA I- Negative Supply Current All Channels V A = 0.8V -0.01 -0.01 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V -0.01 -0.02 µA tOPEN Break-Before-Make Time Delay R L = 300Ω, VS = 3V, VAH = 5V, VAL = 0V 42 47 ns tON Switch Turn “ON” Time R L = 300Ω, VS = 3V, VAH = 4V, VAL = 0V 224 213 ns tOFF Switch Turn “OFF” Time R L = 300Ω, VS = 3V, VAH = 4V, VAL = 0V 192 173 ns Electrical Specifications VSUPPLY = ±15V unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 5) TYP MAX (Note 5) UNITS

5 FN8399.1 April 19, 2013 Post Radiation Characteristics VSUPPLY = ±15V unless otherwise specified. This data is typical test data post radiation exposure at a rate of <10mrad(Si)/s. This data is intended to show typical parameter shifts due to total ionizing dose (low dose radiation). TA= +25°C. SYMBOL PARAMETER TEST CONDITIONS 0k 25k 50k 75k 100k UNITS +IS(OFF) Leakage Current into Source of an “OFF” Switch -IS(OFF) Leakage Current into Source of an “OFF” Switch +ID(OFF) Leakage Current into Drain of an “OFF” Switch -ID(OFF) Leakage Current into Drain of an “OFF” Switch +ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) -ID(ON) Leakage Current from an “ON” Driver into the Switch (Drain and Source) I+ Positive Supply Current All Channels V A = 0.8V 54 51 50 49 50 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V 185 146 129 116 106 µA VA1 = 0V, VA2 = 4V VA1 = 4V, VA2 = 0V

7 FN8399.1 April 19, 2013 Die Characteristics DIE DIMENSIONS: 2815µm x 5325µm (106 milsx205 mils) Thickness: 483µm ± 25.4µm (19 mils ± 1 mil) INTERFACE MATERIALS: Glassivation: Type: PSG (Phosphorous Silicon Glass) Thickness: 8.0kÅ ± 1.0kÅ Top Metallization: Type: AlSiCu Thickness: 16.0kÅ ± 2kÅ Substrate: Radiation Hardened Silicon Gate, Dielectric Isolation Backside Finish: Silicon ASSEMBLY RELATED INFORMATION: Substrate Potential: Unbiased (DI) ADDITIONAL INFORMATION: Worst Case Current Density: <2.0 x 105 A/cm2 Transistor Count: 216 Package Lid Potential: Floating Metallization Mask Layout HS-303CEH IN1 GND IN2 ORIGIN

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 2. LAYOUT X-Y COORDINATES

9 FN8399.1 April 19, 2013 About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the fastest growing markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil or to find out how to become a member of our winning team, visit our website and career page at www.intersil.com. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective product information page. Also, please check the product information page to ensure that you have the most updated datasheet: HS-303CEH To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff Reliability reports are available from our website at: http://rel.intersil.com/reports/search.php

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that you have the latest revision. DATE REVISION CHANGE April 5, 2013 FN8399.1 Title on page 1 changed CMOS to BiCMOS Continuous Current in “Absolute Maximum Ratings” on page 3 changed from 30mA to 10mA “Post Radiation Characteristics” on page 4 changed unit in positive supply current from mA to µA. March 26, 2013 Updated throughout 300krad to 100krad. Updated Ordering Information on page 2 Updated Electrical Spec Table MIN and MAX values for Leakage Current in Source and Drain for ±15V from ±5 to ±20 Updated in Post Radiation Characteristics Typical values on page 4 for Positive Supply Current for VA1, VA2 from 107.1 to 113.7 and Negative Supply Current for VA1, VA2 from -0.01 to -0.02 Added 100k column to Post Radiation Characteristics table on page 5 Removed negative symbol under 75k column IAL, IAH from 0.71, 0.28 and added negative symbol in I- to 0.019 in VA1, VA2 Removed the words exposed pad from Tjc note. Updated numbers in Table 2 in X(µm) column. Added Note to Table 2. December 21, 2012 FN8399.0 Initial Release

10 FN8399.1 April 19, 2013 Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-cent er lid, meniscus, and glass over- run. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the me- niscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E 1 -0 . 2 9 0-7 . 1 13 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 N1 4 1 4- Rev. 0 5/18/94