HS-302RH RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 5

Technical content

Features

  • QML class T, Per MIL-PRF-38535
  • Radiation performance -G a m m a d o s e () 1 x 105 RAD(Si)
  • No latch-up, dielectrically isolated device islands
  • Pin for pin compatible with Intersil HI-302 series analog switches
  • Analog signal range 15V
  • L o w R Pin Configurations HS1-302RH, HS1-302EH (14 LD SBDIP), CDIP2-T14 TOP VIEW HS9-302RH, HS9-302EH (14 LD FLATPACK), CDFP3-F14 TOP VIEW TRUTH TABLE LOGIC ALL SWITCHES 0O F F 1O N N PIN D NC GND IN1 IN2 S2S1 NC GND IN1 IN2 NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc

HS-302RH, HS-302EH FN4603 Rev 3.00 Page 2 of 5 July 31, 2013

Ordering Information

(Note 2) PART NUMBER TEMP. RANGE (°C) PACKAGE (RoHS Compliant) (Note 1) PKG. DWG. # 5962R9581201V9A HS0-302RH-Q -55 to +125 Die 5962R9581204V9A HS0-302EH-Q -55 to +125 Die 5962R9581201QCC HS1-302RH-8 -55 to +125 14 Ld SBDIP D14.3 5962R9581201VCC HS1-302RH-Q -55 to +125 14 Ld SBDIP D14.3 5962R9581204VCC HS1-302EH-Q -55 to +125 14 Ld SBDIP D14.3 5962R9581201QXC HS9-302RH-8 -55 to +125 14 Ld Flatpack K14.A 5962R9581201VXC HS9-302RH-Q -55 to +125 14 Ld Flatpack K14.A 5962R9581204VXC HS9-302EH-Q -55 to +125 14 Ld Flatpack K14.A HS9-302RH/PROTO HS9-302RH/PROTO -55 to +125 14 Ld Flatpack K14.A HS0-302RH/SAMPLE HS0-302RH/SAMPLE -55 to +125 Die NOTES: 1. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 2. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed in the “Ordering Information” table on page 2 must be used when ordering..

FN4603 Rev 3.00 Page 3 of 5 July 31, 2013 HS-302RH, HS-302EH Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Die Characteristics DIE DIMENSIONS: (2130µm x 1930µm x 533µm ±25.4µm) 84 x 76 x 21mils ±1mil METALLIZATION: Type: Al Thickness: 12.5k Å ±2kÅ SUBSTRATE POTENTIAL: Unbiased (DI) BACKSIDE FINISH: Silicon PASSIVATION: Type: Silox (SiO2) Thickness: 8kÅ ±1kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: PROCESS: Metal Gate CMOS, Dielectric Isolation Metallization Mask Layout HS-302RH, HS-302EH IN1 NC GND IN2

HS-302RH, HS-302EH FN4603 Rev 3.00 Page 4 of 5 July 31, 2013 Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 3. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 4. The maximum limits of lead dimensions b and c or M shall be mea- sured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 6. Corner leads (1, N, N/2, and N/2+1) may be configured with a par- tial lead paddle. For this configur ation dimension b3 replaces di- mension b2. 7. Dimension Q shall be measured from the seating plane to the base plane. 8. Measure dimension S1 at all four corners. 9. Measure dimension S2 from the top of the ceramic body to the near- est metallization or lead. 10. N is the maximum number of terminal positions. 11. Braze fillets shall be concave. 12. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 13. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa C A - BM DS Sccc C A - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D14.3 MIL-STD-1835 CDIP2-T14 (D-1, CONFIGURATION C)

14 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE

A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7  90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 4 1 4 8 Rev. 0 4/94

HS-302RH, HS-302EH FN4603 Rev 3.00 Page 5 of 5 July 31, 2013 Ceramic Metal Seal Flatpack Packages (Flatpack) NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. This dimension allows for off-c enter lid, meniscus, and glass over- run. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the me- niscus) of the lead from the bo dy. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-

0.004 H A - BM DS S

-A- -B-

0.036 H A - BM DS S

e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)

14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE

A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E 1 -0 . 2 9 0-7 . 1 13 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 N1 4 1 4- Rev. 0 5/18/94