HS-302AEH RENESAS | Alldatasheet
Document overview
- Manufacturer or author: Renesas Electronics Corporation
- PDF pages: 16
Technical content
HS-302AEH 1. Overview FN8815 Rev.3.0 Page 2 of 15 Jul 7, 2021 1. Overview
1.1 Pin Configuration
1.2 Pin Descriptions
14 Ld Flatpack, CDFP3-F14
Pin Number Pin Name Pin Description
1 NC Not electrically connected
2 S3 Analog switch: source connection
3 D3 Analog switch: drain connection
6 IN1 Digital control input for SW1 and SW3
7 GND Ground
8 V- Negative power supply
9 IN2 Digital control input for SW2 and SW4
14 V+ Positive power supply
N/A LID Electric ally floating NC GND IN1 IN2
HS-302AEH 1. Overview FN8815 Rev.3.0 Page 3 of 15 Jul 7, 2021
1.3 Ordering Information
Number (Note 3) Part Number (Note 2) Radiation Hardness (Total Ionizing Dose) Package (RoHS Compliant) Pkg. Dwg. # Temp. Range 5962R9581205VXC HS9-302AEH-Q HDR to 100krad(Si) LDR to 50krad(Si) 14 Ld Flatpack K14.A -55 to +125°C 5962R9581205V9A HS0-302AEH-Q ( Note 4)D i e N / A N/A HS9-302AEH/PROTO ( Note 5) N/A 14 Ld Flatpack K14.A N/A HS0-302AEH/SAMPLE ( Notes 4, 5)D i e N / A Notes: 2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. 3. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers listed must be used when ordering. 4. Die product tested at T A = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the electrical performance outlined in Electrical Specifications. 5. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a Certificate of Conformance because they are not DLA qualified devices.
HS-302AEH 2. Specifications FN8815 Rev.3.0 Page 4 of 15 Jul 7, 2021 2. Specifications
2.1 Absolute Maximum Ratings
2.2 Thermal Information
2.3 Recommended Operation Conditions
Parameter Minimum Maximum Unit Voltage Between V+ and V- Terminals 35 V ±VSUPPLY to Ground (V+, V-) ±17.5 V Analog Input Voltage (+VS) +VSUPPLY + 1.5 V (-VS) -VSUPPLY - 1.5 V Digital Input Voltage (+VA) +VSUPPLY + 4 V (-VA) -VSUPPLY - 4 V Peak Current (S or D), (Pulse at 1ms, 10% Duty Cycle Max) 40 mA Continuous Current 10 mA ESD Rating Value Unit Human Body Model (Tested per MIL-PRF-883 TM 3015.7) 2 kV Machine Model (Tested per EIA/JESD22-A115-A) 200 V Charged Device Model (Tested per JESD22-C101D) 1 kV CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty. Thermal Resistance (Typical) θ JA (°C/W) θJC (°C/W) Flatpack Package (Notes 6, 7) 105 17 Notes: 6. θJA is measured in free air with the component mounted on a low-effective thermal conductivity test board in free air. See TB379. 7. For θJC, the “case temp” location is the center of the package underside. Parameter Minimum Maximum Unit Package Power Dissipation at 125°C, Flatpack Package 0.48 W Junction Temperature (TJ) +175 °C Storage Temperature Range -65 +150 °C Parameter Minimum Maximum Unit Operating Temperature Range -55 +125 °C Operating Supply Voltage Range (±VSUPPLY)± 1 5 V Analog Input Voltage (VS) ±VSUPPLY V Logic Low Level (VAL)0 0 . 8 V Logic High Level (VAH)4 . 0 + V SUPPLY V
HS-302AEH 2. Specifications FN8815 Rev.3.0 Page 5 of 15 Jul 7, 2021
2.4 Electrical Specifications
VSUPPLY = ±15V unless otherwise specified. Boldface limits either apply across the operating temperature range -55°C to +125°C or across a total ionizing dose of 100krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s and a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. Parameter Symbol Test Conditions Min (Note 8)T y p Max (Note 8) Unit Switch On-Resistance +r DS(ON) VD = 10V, IS = -10mA, TA = +25°C - - 50 Ω TA = -55°C to +125°C - 35 75 Ω TA = 25°C, post radiation - - 60 Ω Switch On-Resistance -r DS(ON) VD = -10V, IS = 10mA, TA = +25°C - - 50 Ω TA = -55°C to +125°C - 35 75 Ω TA = 25°C, post radiation - - 60 Ω Leakage Current into Source Terminal of an OFF Switch +IS(OFF) VS = +14V, VD = -14V, TA = +25°C -100 - 100 nA VS = +14V, VD = -14V, TA = -55°C to +125°C -150 0.05 150 nA VS = +14V, VD = -14V, TA = +25°C, post radiation -150 - 150 nA VS = +15V, VD = -15V, TA = +25°C -1 - 1 µA VS = +15V, VD = -15V, TA = -55°C to +125°C -20 - 20 µA VS = +15V, VD = -15V, TA = +25°C, post radiation -20 - 20 µA Leakage Current into Source Terminal of an OFF Switch -IS(OFF) VS = -14V, VD = +14V, TA = +25°C -100 - 100 nA VS = -14V, VD = +14V, TA = -55°C to +125°C -150 0.05 150 nA VS = -14V, VD = +14V, TA = +25°C, post radiation -150 - 150 nA VS = -15V, VD = +15V, TA = +25°C -1 - 1 µA VS = -15V, VD = +15V, TA = -55°C to +125°C -20 - 20 µA VS = -15V, VD = +15V, TA = +25°C, post radiation -20 - 20 µA Leakage Current into Drain Terminal of an OFF Switch +ID(OFF) VS = +14V, VD = -14V, TA = +25°C -100 - 100 nA VS = +14V, VD = -14V, TA = -55°C to +125°C -150 0.05 150 nA VS = +14V, VD = -14V, TA = +25°C, post radiation -150 - 150 nA VS = +15V, VD = -15V, TA = +25°C -1 - 1 µA VS = +15V, VD = -15V, TA = -55°C to +125°C -20 - 20 µA VS = +15V, VD = -15V, TA = +25°C, post radiation -20 - 20 µA Leakage Current into Drain Terminal of an OFF Switch -ID(OFF) VS = -14V, VD = +14V, TA = +25°C -100 - 100 nA VS = -14V, VD = +14V, TA = -55°C to +125°C -150 0.5 150 nA VS = -14V, VD = +14V, TA = +25°C, post radiation -150 - 150 nA VS = -15V, VD = +15V, TA = +25°C -1 - 1 µA VS = -15V, VD = +15V, TA = -55°C to +125°C -20 - 20 µA VS = -15V, VD = +15V, TA = +25°C, post radiation -20 - 20 µA Leakage Current from an ON Driver into the Switch (Drain and Source) +ID(ON) VS = +14V, VD = +14V, TA = +25°C -20 - 20 nA VS = +14V, VD = +14V, TA = -55°C to +125°C -100 -0.1 100 nA VS = +14V, VD = +14V, TA = +25°C, post radiation -100 - 100 nA Leakage Current from an ON Driver into the Switch (Drain and Source) -ID(ON) VS = -14V, VD = -14V, TA = +25°C -20 - 20 nA VS = -14V, VD = -14V, TA = -55°C to +125°C -100 -0.1 100 nA VS = -14V, VD = -14V, TA = +25°C, post radiation -100 - 100 nA
HS-302AEH 2. Specifications FN8815 Rev.3.0 Page 6 of 15 Jul 7, 2021 Low Level Input Address Current I AL All Channels VA = 0.8V, TA = -55°C to +125°C -1 - 1 µA All Channels VA = 0.8V, TA = +25°C, post radiation -1 - 1 µA High Level Input Address Current I AH All Channels VA = 4.0V, TA = -55°C to +125°C -1 - 1 µA All Channels VA = 4.0V, TA = +25°C, post radiation -1 - 1 µA Positive Supply Current I+ All Channels V A = 0.8V, TA = +25°C - - 100 µA All Channels VA = 0.8V, TA = -55°C to +125°C - 45 150 µA All Channels VA = 0.8V, TA = +25°C, post radiation -- 150 µA VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA =+ 2 5 ° C -- 0 . 4 m A VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA = -55°C to +125°C -0 . 1 5 0.6 mA VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA = +25°C, post radiation -- 0.6 mA Negative Supply Current I- All Channels V A = 0.8V, TA = +25°C - - -10 µA All Channels VA = 0.8V, TA = -55°C to +125°C - -0.1 -100 µA All Channels VA = 0.8V, TA = +25°C, post radiation -- -100 µA VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA =+ 2 5 ° C -- - 1 0 µ A VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA = -55°C to +125°C -- 0 . 1 -100 µA VA1 = 0V, VA2 = 4V, VA1 = 4V, VA2 = 0V, TA = +25°C, post radiation -- -100 µA Switch Input Capacitance C IS(OFF) From Source to GND (Note 9)- - 2 8 p F Driver Input Capacitance C C1 VA = 0V (Note 9)- - 1 0 p F Driver Input Capacitance C C2 VA = 15V (Note 9)- - 1 0 p F Switch Output C OS Measured Drain to GND (Note 9)- - 3 2 p F Off Isolation V ISO VGEN = 1VP-P, f = 1MHz (Note 9)4 0 - - d B Cross Talk V CR VGEN = 1VP-P, f = 1MHz (Note 9)4 0 - - d B Charge Transfer Error V CTE VS = GND, CL= 0.01µF (Note 9)- - 1 5 m V Switch Turn-On Time t ON RL = 300Ω, VS = 3V, VAH = 4V, VAL = 0V, TA = +25°C - - 375 ns TA = -55°C to +125°C - 250 500 ns TA = +25°C, post radiation - - 1 µs Switch Turn-Off Time t OFF RL = 300Ω, VS = 3V, VAH = 4V, VAL = 0V - - 300 ns TA = -55°C to +125°C - 200 450 ns TA = +25°C, post radiation - - 1 µs Notes: 8. Compliance to datasheet limits is as sured by one or more methods: production test, characterization, and/or design. 9. V AL = 0V and VAH = 4V. VSUPPLY = ±15V unless otherwise specified. Boldface limits either apply across the operating temperature range -55°C to +125°C or across a total ionizing dose of 100krad(Si) with exposure of a high dose rate of 50 to 300rad(Si)/s and a total ionizing dose of 50krad(Si) with exposure at a low dose rate of <10mrad(Si)/s. (Continued) Parameter Symbol Test Conditions Min (Note 8)T y p Max (Note 8) Unit
- Test Circuits and Waveforms
3.1 Switching Times
Figure 3. Switching Times Measurement Points Figure 4. Switching Times Test Circuit Figure 5. Charge Transfer Error Measurement Points Figure 6. Charge Transfer Error Test Circuit Figure 7. Off Isolation Test Circuit Figure 8. r ON Test Circuit V-Repeat test for all switches. V-Repeat test for all switches.
Figure 9. Crosstalk Test Circuit Fig ure 10. Capacitance Test Circuit
Table 2. Die and Assembly Related Information
5 A/cm2
HS-302AEH 6. Metalliz ation Mask Layout FN8815 Rev.3.0 Page 12 of 15 Jul 7, 2021 6. Metallization Mask Layout D3 (3) S1 (5) IN1 (6) GND (7) D4 (12) D2 (11) S2 (10) IN2 (9) V- (8) D1 (4) Origin
6.1 Layout Characteristics
Table 3. Layout X-Y Coordinates Note: “Origin” as labeled in the Metallization Mask layout is the centroid of the pad labeled “IN1”.
HS-302AEH 7. Revision History FN8815 Rev.3.0 Page 14 of 15 Jul 7, 2021 7. Revision History Date Revision Change Jul 7, 2021 3.0 Removed Related Literature section. Updated Ordering information table format, added Rad hard information, and updated notes. On page 11 in table 2, Die Characteristics in the Dimensions row change from (106mils x 205mils) to (110.83mils x 209.65mils). Jul 18, 2019 2.0 Updated single event effects information on page 1. Updated links. Removed About Intersil section. Applied new template. Mar 17, 2017 1.0 Changed the title from “CMOS” to “BiCMOS” Added “Related Literature” section Added Note 5. Jul 15, 2016 0.0 Initial release
HS-302AEH 8. Package Outline Drawing FN8815 Rev.3.0 Page 15 of 15 Jul 7, 2021 8. Package Outline Drawing For the most recent package outline drawing, see K14.A. NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the lim- its of dimension k do not apply. 3. This dimension allows for off-center lid, meniscus, and glass overrun. 4. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. The maximum lim- its of lead dimensions b and c or M shall be measured at the cen- troid of the finished lead surfac es, when solder dip or tin plate lead finish is applied. 5. N is the maximum number of terminal positions. 6. Measure dimension S1 at all four corners. 7. For bottom-brazed lead packages, no organic or polymeric mate- rials shall be molded to the bottom of the package to cover the leads. 8. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when sol- der dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH. -D- -C-
0.004 H A - BM DS S
-A- -B-
0.036 H A - BM DS S
e E A Q L D A SEATING AND LE2 E3 E3 BASE PLANE -H- b C M (c) (b) SECTION A-A BASE LEAD FINISH METAL PIN NO. 1 ID AREA A M K14.A MIL-STD-1835 CDFP3-F14 (F-2A, CONFIGURATION B)
14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - D - 0.390 - 9.91 3 E 0.235 0.260 5.97 6.60 - E 1 -0 . 2 9 0 -7 . 1 1 3 E3 0.030 - 0.76 - 7 e 0.050 BSC 1.27 BSC - k 0.008 0.015 0.20 0.38 2 L 0.270 0.370 6.86 9.40 - Q 0.026 0.045 0.66 1.14 8 S1 0.005 - 0.13 - 6 N1 4 1 4- Rev. 0 5/18/94
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