HS-26CLV32RH RENESAS | Alldatasheet
Document overview
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- PDF pages: 13
Technical content
Datasheet sections
- 1.1 Pin Assignments
- 1.2 Pin Descriptions
- 2.1 Absolute Maximum Ratings
- 2.2 Recommended Operating Conditions
- 2.3 Thermal Specifications
- 2.4 Electrical Specifications
- 4.1 Metallization Mask Layout
Features
▪ Electrically screened to SMD # 5962-95689 ▪ QML qualified per MIL-PRF-38535 requirements ▪ 1.2 micron radiation hardened CMOS ▪ Low stand-by current: 13mA (max) ▪ Operating supply range: 3.0V to 3.6V ▪ Differential input voltage thresholds: ±400mV ▪ CMOS output levels: VOH > 2.55V, VOL < 0.4V ▪ Input fail-safe circuitry ▪ High impedance inputs when disabled or powered- down ▪ Radiation acceptance testing ‒ HS-26CLV32RH
- HDR (50-300rad (Si)/s): 300krad(Si) ▪ Radiation acceptance testing ‒ HS-26CLV32EH
- HDR (50-300rad(Si)/ s): 300krad(Si)
- LDR (0.01rad(Si)/s): 50krad(Si) ▪ SEL immune to LET: 100MeV•cm2/mg ▪ Full -55°C to +125°C military temperature range ▪ Pb-free (RoHS compliant) HS-26CLV32RH, HS-26CLV32EH Radiation Hardened 3.3V Quad Differential Line Receivers
1.1 Pin Assignments
1.2 Pin Descriptions
Figure 1. 16 LD SBDIP, MIL-STD-1835: CDIP2-T16
- For details on the input output structures, refer to AN9520.
- For details on the package dimensions, refer to MIL-STD-1835.
Figure 2. 16 LD FLATPACK, MIL-STD-1835: CDFP4-F16
- For 16 Ld Flatpack, there are two options; 1) Lid not grounded (noted as Case X in SMD and 2) Lid is grounded (noted as Case Y in SMD).
10 DIN
11 DOUT
12 ENABLE
13 BOUT
14 BIN
15 BIN
16 VDD
Figure 3. Logic Diagram Table 1. Truth Table
FN4907 Rev.7.01 Page 5 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet 2. Specifications
2.1 Absolute Maximum Ratings
Caution: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
2.2 Recommended Operating Conditions
2.3 Thermal Specifications
Parameter Minimum Maximum Unit Supply Voltage -0.5 +7.0 V Differential Input Voltage -12 +12 V Common Mode Range -12 +12 V Enable Pins Input Voltage -0.5 V DD + 0.5 V DC Drain Current (any one output) -25 +25 mA DC Diode Input Current Enable Pin -20 +20 mA Maximum Package Power Dissipation at T A = +125°C 16 Ld SBDIP - 0.6 W 16 Ld Flatpack - 0.5 W Maximum Device Power Dissipation (PD)[1] 1. Maximum device power dissipation is defined as V DD x ICC and must withstand the added PD due to output current test; IO at TA = +125°C. -0 . 3 2 W Human Body Model (Tested per MIL-PRF-883 3015.7) - 750 V Parameter Minimum Maximum Unit Ambient Temperature Range -55 +125 °C V DD Supply Voltage +3.0 +3.6 V Common Mode Range -4.0 +7.0 V Input Low Voltage (V IL) 0 0.3 V DD max V Input High Voltage (VIH)V DD +0.7 VDD min V Input Rise and Fall Time - 500 ns Parameter Package Symbol Conditions Typical Value Unit Thermal Resistance 16 Ld Flatpack Package θJA[1] 1. θJA is measured with the component mounted on a low-effective thermal conductivity test board. See TB379 for details. Junction to ambient 103 °C/W θJC[2] 2. For θJC, the case temperature location is the center of the package underside. Junction to case 26 °C/W Thermal Resistance 16 Ld SBDIP Package θJA[1] Junction to ambient 80 °C/W θJC[2] Junction to case 20 °C/W
FN4907 Rev.7.01 Page 6 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet
2.4 Electrical Specifications
Test Conditions: VDD = 3.0V to 3.6V; Typical values are at TA = +25°C; unless otherwise specified[2]. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 50krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s; and over a total ionizing dose of 300krad(SI) at +25°C with exposure of a high dose rate of 50krad(SI)/s to 300krad(SI)/s. Parameter Symbol Test Conditions Temp (°C) Min [1] 1. Parameters with Min and/or Max Limits are 100% tested at -55°C, +25°C, and +125°C, unless otherwise specified. Typ[2] Max[1] Unit High Level Output Voltage V OH VDD = 3.0V, VDIFF = 1.0V, IO = -6mA[3] 3. V IL = 0.3VDD, VIH = 0.7VDD. Full 2.55 -- V Low Level Output Voltage V OL VDD = 3.0V, VDIFF = -1.0V, IO = 6mA[3] Full - - 0.4 V Input Voltage Threshold (Differential Input) VTH VDD = VIH = 3.0V, -4.0V < VCM < 7.0V Full -400 - +400 mV High Level Input Voltage (Logic Inputs) VIH VDD = 3.0V, 3.6V[4] 4. This parameter tested as inputs for the V OL and VOH tests. Full 0.7 VDD -- V Low Level Input Voltage (Logic Inputs) VIL VDD = 3.0V, 3.6V[4] Full - - 0.3 VDD V Input Current High (Differential Inputs) IINH VDD = 3.6V, +V = 10V, -V = 0V and +V = 0V, -V = 10V Full - - 1.8 mA Input Current Low (Differential Inputs) IINL VDD = 3.6V, +V = -10V, -V = 0V and +V = 0V, -V = -10V Full -2.7 -- m A Input Leakage Current, Enable Pins IIN VDD = 3.6V, VIN = 0V, 3.6V Full -1.0 - +1.0 µA Three-state Output Leakage Current IOZ VDD = 3.6V, VO = VDD or GND Full -5.0 - 5.0 µA Standby Supply Current I DDSB VDD = 3.6V, VDIFF = 1.0V, Outputs = open Full - - 13 mA Enable Clamp Voltage V IC At - 1mA Full -1.5 -- V At 1mA Full - - +1.5 Input Hysteresis V HYST -F u l l 20[5] 5. If not tested, it is guaranteed to the limits specified. - 100 mV Input Resistance R IN -4.0V < VCM < 7.0V Full 4 - 20 kΩ Propagation Delay Time[6] 6. Reference EIA RS-422. tPLH, tPHL VDD = 3.0V, VDIFF = 2.5V, See Figure 5 through Figure 8. Full 6 - 65 nstPZH, tPZL Full 3 - 40 tPHZ, tPLZ Full 6 - 38 Propagation Delay Time,[6] tRISE/tFALL tTHL tTLH VDD = 3.0V, VDIFF =2 . 5 V F u l l 2 - 15 ns Input Capacitance[7] 7. Parameter is guaranteed by design or process, but not tested. CIN VDD = open, f - 1MHz Full - - 12 pF Output Capacitance[7] COUT VDD = open, f - 1MHz Full - - 12 pF Fail Safe F SAFE + and - Inputs are open, VOUT = logic “1” Full 2.55 -- V
4.1 Metallization Mask Layout
Table 2. Die and Assembly Related Information Table 3. HS-26CLV32RH, HS-26CLV32EH
FN4907 Rev.7.01 Page 9 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet 5. Package Outline Drawings For the most recent package outline drawing, see K16.A.
16 Lead Ceramic Metal Seal Flatpack Package
Rev 2, 1/10 SIDE VIEW TOP VIEW SECTION A-A -D- -C- SEATING AND BASE PLANE -H- BASE LEAD FINISH METAL PIN NO. 1 ID AREA 0.022 (0.56) 0.015 (0.38) 0.050 (1.27 BSC) 0.440 (11.18) 0.005 (0.13) MIN MAX 0.115 (2.92) 0.026 (0.66) 0.285 (7.24) 0.245 (6.22) 0.009 (0.23) 0.004 (0.10) 0.370 (9.40) 0.250 (6.35) 0.03 (0.76) MIN 0.13 (3.30) MIN 0.006 (0.15) 0.004 (0.10) 0.009 (0.23) 0.004 (0.10) 0.019 (0.48) 0.015 (0.38) 0.0015 (0.04) MAX 0.022 (0.56) 0.015 (0.38) 0.015 (0.38) 0.008 (0.20) PIN NO. 1 ID OPTIONAL 1 2 LEAD FINISH adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. Alternately, a tab may be used to identify pin one. of the tab dimension do not apply. 3. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. shall be molded to the bottom of the package to cover the leads. meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. NOTES: Dimensioning and tolerancing per ANSI Y14.5M - 1982. Controlling dimension: INCH. Index area: A notch or a pin one identification mark shall be located If a pin one identification mark is used in addition to a tab, the limits Measure dimension at all four corners. For bottom-brazed lead packages, no organic or polymeric materials Dimension shall be measured at the point of exit (beyond the
FN4907 Rev.7.01 Page 10 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet For the most recent package outline drawing, see D16.3. Ceramic Dual-In-Line Metal Seal Packages (SBDIP) NOTES: 1. Index area: A notch or a pin one identification mark shall be locat- ed adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be mea- sured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a par- tial lead paddle. For this configur ation dimension b3 replaces di- mension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH. bbb C A - BS c Q L A SEATING BASE D PLANE PLANE S S -D--A- -C- eA -B- aaa CA - BM DS Sccc CA - BM DS S D E b A e M (c) (b) SECTION A-A BASE LEAD FINISH METAL eA/2 M A D16.3 MIL-STD-1835 CDIP2-T16 (D-2, CONFIGURATION C)
16 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE
A - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 E 0.220 0.310 5.59 7.87 - e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 5 S1 0.005 - 0.13 - 6 S2 0.005 - 0.13 - 7 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2 N1 6 1 68 Rev. 0 4/94
FN4907 Rev.7.01 Page 11 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet 6. Ordering Information Ordering SMD Number[1] 1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbe rs listed must be used when ordering. Part Number[2] 2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Radiation Hardness (Total Ionizing Dose) Package Description (RoHS Compliant) Pkg. Dwg. # Carrier Type Temp. Range 5962F9568902QEC HS1-26CLV32RH-8 HDR to 300krad(Si) 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9568902QXC HS9-26CLV32RH-8 16 Ld Flatpack K16.A Tray -55 to +125°C 5962F9568902VEC HS1-26CLV32RH-Q 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9568902VXC HS9-26CLV32RH-Q 16 Ld Flatpack K16.A Tray -55 to +125°C 5962F9568902V9A HS0-26CLV32RH-Q [3] 3. Die product tested at T A = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the electrical performance outlined in SMD. Die N/A N/A -55 to +125°C 5962F9568902VYC HS9G-26CLV32RH-Q [4] 4. The lid of these packages are connected to the ground pin of the device. 16 Ld Flatpack K16.A Tray -55 to +125°C N/A HS0-26CLV32RH/SAMPLE[3][5] 5. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across the temperature range specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a certificate of conformance because they are not DLA qualified devices. N/A Die N/A N/A -55 to +125°C HS1-26CLV32RH/PROTO[5] 16 Ld SBDIP D16.3 Tube -55 to +125°C HS9-26CLV32RH/PROTO[5] 16 Ld Flatpack K16.A Tray -55 to +125°C HS9G-26CLV32RH/PROTO[4][5] 16 Ld Flatpack K16.A Tray -55 to +125°C 5962F9568904VEC HS1-26CLV32EH-Q HDR to 300krad(Si) LDR to 50krad(Si) 16 Ld SBDIP D16.3 Tube -55 to +125°C 5962F9568904VXC HS9-26CLV32EH-Q 16 Ld Flatpack K16.A Tray -55 to +125°C 5962F9568904V9A HS0-26CLV32EH-Q [3] Die N/A N/A -55 to +125°C 5962F9568904VYC HS9G-26CLV32EH-Q [4] 16 Ld Flatpack K16.A Tray -55 to +125°C
FN4907 Rev.7.01 Page 12 May 14, 2025 HS-26CLV32RH, HS-26CLV32EH Datasheet 7. Revision History Revision Date Description
7.01 May 14, 2025
Applied latest template. Added Pin Information, ABS Max Ratings, Thermal Info, and Electrical Specifications sections. Updated timing and load circuit diagrams.
7.00 Oct 21, 2021
Removed Related Literature section. In Features section on page 1 added Radiation acceptance testing bullets for RH and EH parts. In Ordering Information table on page 2 verified the part numbers in the table are correct, added carrier type and radiation testing information columns, and re-ordered the notes in the table and added notes 3 and 5. Added Truth Table, Timing Diagrams, and Load Circuit Diagrams. Updated the Die Characteristics information as follows: -Changed the die thickness from: 21mils, to: 19mils -Updated Worst Case Current Density. -Added Transistor count. Removed About Intersil section.
6.00 Feb 6, 2017
Added Related Literature section. Updated Ordering Information table on page 2. Added Note 2 on page 2. Added Revision History and About Intersil sections. Added POD drawings.
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